Manual

Industrial Grade 203 Series IDE DOM Product Manual v2.0Cactus Technologies
®
16
The communication to or from the DOM is done using the Task File registers, which provide all the
necessary registers for control and status information. The ATA interface connects peripherals to the
host using four register mapping methods. Table 4-8 is a detailed description of these methods.
Task File Addressing
4.1.
Table 4-8. I/O Congurations
Table 4-9. Task File I/O Decoding
Address Drive # Description
1F0-1F7, 3F6-3F7 0 Primary I/O Mapped Drive 0
1F0-1F7, 3F6-3F7 1 Primary I/O Mapped Drive 1
170-177, 376-377 0 Secondary I/O Mapped Drive 0
170-177, 376-377 1 Secondary I/O Mapped Drive 1
-CE2 -CE1 A2 A1 A0 -IORD=0 -IOWR=0
1 0 0 0 0 RD Data WR Data
1 0 0 0 1 Error Register Features
1 0 0 1 0 Sector Count Sector Count
1 0 0 1 1 Sector No. Sector No.
1 0 1 0 0 Cylinder Low Cylinder Low
1 0 1 0 1 Cylinder High Cylinder High
1 0 1 1 0 Select Drive/Head Select Drive/Head
1 0 1 1 1 Status Command
0 1 1 1 0 Alt Status Device Control
0 1 1 1 1 Drive Address Reserved
ATA Drive Register Set
Denition and Protocol04
I/O decoding to access the task le registers is as listed in Table 4-9.