User guide

203 Series Industrial Grade 2.5" FlashDrive Product Manual v2.0Cactus Technologies

Bit 7 This bit is an X (Do not care).

Bit 6 This bit is an X (Do not care).

Bit 5 This bit is an X (Do not care).

Bit 4 This bit is an X (Do not care).

Bit 3 This bit is ignored by the drive.

Bit 2 (SW Rst) This bit is set to 1 in order to force the drive to perform an AT Disk controller

Soft Reset operation. The drive remains in Reset until this bit is reset to '0'.

Bit 1 (-IEn) The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,

interrupts from the drive are disabled. This bit is set to 0 at power on and Reset.

Bit 0 This bit is ignored by the drive.

4.2.11. Drive Address Register (Address 3F7[377])

This register is provided for compatibility with the AT disk drive interface. It is recommended that

this register not be mapped into the host's I/O space because of potential conicts on Bit 7. The bits

are dened as follows:

D7 D6 D5 D4 D3 D2 D1 D0

X -WTG -HS3 -HS2 -HS1 -HS0 -nDS1 -nDS0