Specifications

Application Views Fore Software Application (ForeSoftWreApp)
Device Management Page 79 ForeRunner ATM Switch Modules
UBR Taggin
This variable defines the per-port configuration
for tagging (setting CLP=1) of all cells on UBR
connections. The states are defined in Table 26.
Input Delay Mode
Allows you to control whether the Cell Delay
Variation and Maximum Cell Transfer Delay
values attributed to the input side of this port are
based on a user defined value of the hardware
dependent system default values. Options are
systemDefault or userSpecified.
Output Delay Mode
Allows you to control whether the Cell Delay
Variation value contributed by the input side of
this port is based on a user defined value or the
system default value.
CAC Status
The enforcement state of call admission control,
either enabled or disabled. The default is
enabled.
Path Routes of Selected Port View
Access: Within the ATM Switch Software Port Detail
View, click the Path Routes of this Port button.
Path Route Table
A table of information about the routing of paths
through this ATM switch.
In Port
Identifies the input port of this path and is the
same as the port number.
In VPI
The input VPI of this path.
Out Port
The output port of this path.
Out VPI
The output VPI of this path.
Table 26: UBR Connection Tagging States
State Definition
allOn All UBR connections will be
tagged.
allOff No UBR connections will be
subject to tagging.
svcOn All UBR SVC’s will be
tagged. UBR PVC’s will be
tagged based on their UPC
contract.
svcOff No UBR SVC’s will be
tagged. UBR PVCs will be
tagged based on their UPC
contract.