Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 17/30
9es3s1c1.doc
Rev 5.9
02/12/2003
PPC
Address
Bus
DPCIev
CPU 3
CPU 2
CPU 1
CPU 0
DCBev
DIMM
based
Memory
Array
PCI/ISA
slots
Data path 1
Data path 0
Memor
y
addr & ctl
MPIC
DCBev
MSC
PowerScale/Flex Reference Implementation Bus Architecture
The above diagram illustrates the motherboard PowerScale/Flex ASIC set.
DCBev Data Cross Bar for Escala T Series (2 ASICs required)
MSC Memory System Controller
DPCIev Dual Peripheral Component Interconnect
MPIC Multi PCI Interrupt Controller
The system data bus has been divided into 2 separate paths with one being used exclusively by the
CPUs and the other being reserved for the system I/O.
The CPU data path can support up to 4 agents (CPUs).