Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 16/30
9es3s1c1.doc
Rev 5.9
02/12/2003
The above diagram illustrates the motherboard PowerScale/4 ASIC set.
DCBK Data Cross Bar for Escala T Series (2 ASICs required)
SMC2 System Memory Controller
ARB System Arbiter
DPCI Dual Peripheral Component Interconnect
MPIC Multi PCI Interrupt Controller
There are two additional ASICs that are required per CPU board for a PowerPC 604e based system.
These are:
CCA2 Cache Controller Address
CCDK Cache Controller Data for Escala T Series
On a PowerPC 620 based system these additional ASICs are not required since the 620 processors will
interface directly with the PowerPC 6XX bus implemented inside Escala T Series.
The system data bus has been divided into 2 separate paths with one being used exclusively by the
CPUs and the other being reserved for the system I/O.
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The CPU data path can support up to 4 agents (CPUs).
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The I/O data path has been implemented on the T604e/T620 motherboard to support up to 2 agents.
The first agent is the DPCI and the second agent has been left as an open I/O slot on the board. Bull
will create various add-in card options to plug into this slot such as: an additional DPCI option; a high
speed inter-system link controller for clustering and there will be other options created in the future.
This slot is also open for Bull partners to develop options for, remember that it is an opening directly
on the PowerPC 6XX bus and is therefore a very high speed point of entry into the architecture.
1.12.3. PowerScale/Flex Architecture
The PowerScale/Flex chipset is an evolution of the PowerScale/4 and PowerScale/2 chipset to provide
support for PowerPC RS64 processors. This design has been implemented to meet schedule and
price/performance objectives.
The evolution towards PowerPC RS64 processors does not require a new cabinet design, as far as
available power requirements, power dissipation and ventilation is concerned. Therefore, the Escala
T604e/T620 cabinet can be used to enclose the new 4-processor board with integrated I/O.
ASICs pin number will be kept within today Max available solutions (750 pins); consequently the I/O
data channel of the chipset implementation will be kept at 64 bits (DPCIev). The technology used for
ASIC integration is the LSI Logic G10 for the first run and will be replaced by the LSI Logic G11 for
the second run.