Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 15/30
9es3s1c1.doc
Rev 5.9
02/12/2003
1.12.2. PowerScale/4 Architecture
The PowerScale/4 Architecture, designed by Bull, is a high performance 1 to 4-way symmetric
processing architecture designed for the PowerPC 604e and PowerPC 620 microprocessors.
PowerScale/4 is a traditional SMP design with a split transaction approach to the bus architecture.
Crossbar
Memory
Dual I/O Controller
PPC
PowerPC data buses
PPC PPC PPC
Open I/O Slot
PowerScale/4 Architecture
The architecture distinguishes itself in that the system data bus has been divided into 2 separate paths
with one being used exclusively by the CPUs and the other being reserved for the system I/O.
•
The CPU data path can support up to 4 agents (CPUs).
•
The I/O data path has been implemented on the reference platform motherboard to support 2
agents, although the chipset also supports up to 4 I/O agents.
This unique feature permits a high degree of hardware parallelism to occur during system I/O
operations and means that the architecture is ideally suited for applications demanding high I/O traffic.
PPC
address
bus
DPCI
I/O slot
CPU 3
CPU 2
CPU 1
CPU 0
DCBK
DIMM
based
mem
array
PCI/ISA
slots
data path 1
data path 0
memory addr & ctl
SMC2
ARB
MPIC
DCBK
PowerScale/4 Reference Implementation Bus Architecture