Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 14/30
9es3s1c1.doc
Rev 5.9
02/12/2003
Scalability is also a key design consideration. The Escala servers can be easily upgraded. The
packaging permits convenient replacement or upgrading of processor, memory, or I/O adapters. For
example, the processors are contained on processor boards that plug into slots on the system board. A
processor board contains two processors, and upgrading from a two-way system is a matter of
plugging in an additional processor board.
The AIX® operating system provides reliability and serviceability with such features as the Logical
Volume Manager, Journalized File System and dynamic kernel all contributing to a reliable and robust
operating system implementation.
1.12.1. PowerScale/2 Architecture
The PowerScale/2 Architecture, designed by Bull, is an entry high performance 1 to 2-way symmetric
processing architecture designed for the PowerPC 604e and PowerPC 620 microprocessors.
PowerScale/2 is a traditional SMP design with a split transaction approach to the bus architecture.
The “intelligence” center of the architecture is the PMC (PCI & Memory Controller) which integrates
the coherency engine of the SMP design and manages all of the system buses (address & control,
memory data path & control, system data bus and the PCI bus).
The MDP (Memory Data Path) ASICs are used to switch the data to/from the memory array. They also
contain buffering logic and are responsible for the ECC handling on the memory DIMMs.
Illustrated below is the basic bus structure supported by the PowerScale/2 chipset.
PMC
CPU0
CPU1
CPU2
CPU3
MDP
MDP
DIMM
based
mem
array
Address &
control bus
Data bus
64 bit
64 bit
MDP & Mem control
PCI
bus
PowerScale/2 Logical Bus Architecture