Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 12/30
9es3s1c1.doc
Rev 5.9
02/12/2003
1.11. Escala Tower PL, E and T PowerPC System Structure
Many different system designs are available with the PowerPC processor.
The Escala Tower PL, E and T servers are designed to achieve performance scalability and high
availability from the PowerPC processor chip.
One of the major features of the Escala design is the symmetric multiprocessor architecture that allows
to progressively upgrade the system by adding processors. The processors coordinate and share access
to the various system resources (for example, memory and I/O).
1.12. PowerScale Architecture - PowerPC SMP Design
The Escala symmetric multiprocessor (SMP) design incorporates multiple processors sharing a single,
common memory and a single copy of the AIX® operating system. Jobs are scheduled across the
processors, allowing separate processes to be run simultaneously. Data and instructions are accessed
from the shared memory through a high-speed cache to the processors. This simple design with a
coherent memory allows programs to exploit the parallelism provided by the multiple processors.
There are several requirements that the design of a multiprocessor system must satisfy when compared
to a uniprocessor system:
•
Provide for scheduling of separate jobs across the various processors.
•
Provide for synchronization of those separate jobs.
•
Provide efficient paths between each processor and the memory subsystem.
•
Manage the processor caches to maintain cache coherency (consistency).
•
Provide an input/output interface to the memory subsystem.
There are several additional requirements placed on the design by the unique characteristics of
commercial applications. The key to delivering good commercial performance is not a factor solely of
the processor, but rather of the memory hierarchy and the ability to do rapid cache-to-cache transfers.
Typically, commercial applications exhibit data access patterns with a large "footprint". This is
different from scientific or technical work. Commercial workloads are characterized by high L1/L2
cache miss rates, heavy memory traffic, and high cache migration rates. As data traffic increases due to
the large footprint of commercial workloads, it is evident that the memory bus is potentially a
bottleneck. It is, therefore, critical to performance that the SMP system be designed to handle these
applications.
In a traditional SMP architecture the interconnection between CPU caches and global memory is met
by means of a common memory bus shared amongst the various resources. This is typically the weak
point of the system design and will tend to become saturated as the number of processors installed is
increased. This is because the data traffic between caches and memory increases as well as the cache to
cache transfers and they all compete for bandwidth on the memory bus.
Bull PowerScale
™
architecture implements the memory interface in a manner designed to anticipate
the above application profile and to exploit the forthcoming generations of even higher performance
microprocessors.