Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 10/30
9es3s1c1.doc
Rev 5.9
02/12/2003
1.7. PowerPC RS64-III Processors
The RS64 III processor has separate internal 128 KB L1 caches for instructions and data. Both L1
caches have doubled in size over the RS64-II. It contains an L2 cache controller and a dedicated 32-
byte interface to a private 4-way set associative L2 cache. The L2 cache controller supports up to 8
MB L2 cache. The L2 interface runs at half processor speed, but transfers data twice per cycle to
provide 14.4 GB/s of bandwidth. RS64 III internal data paths are 32 bytes wide. The RS64 III
processor also has a separate 16-byte system bus interface.
The RS64-III has a total of five pipeline execution units. There is a Branch Unit, a Load/Store Unit, a
Fixed-point Unit, a Complex Fixed-point Unit and a Floating-point Unit. The processor has a 32-byte
interface to the dispatch logic. There is a current instruction stream dispatch buffer that is 16
instructions deep. The RS64-III has an eight deep branch buffer. The RS64-III can sustain a decode
and execution rate of up to 4 instructions per cycle.
All of the arrays in the RS64-III have either redundancy and ECC or parity and retry to support the
high requirements desired for customer reliability, availability and integrity. This enables full fault
detection and correction coverage.
1.8. PowerPC RS64-IV Processors
The RS64 IV superscalar processors are well optimized for commercial workloads. Target
environments are characterized by heavy demands on system memory, both in the form of very large
working sets and latency-sensitive serial dependencies. As a result, the design of the RS64 IV
processors is focused on large cache sizes and data paths having high bandwidth and low latency.
The RS64 IV processor has separate internal 128KB L1 caches for instructions and data. It contains an
L2 cache controller and a dedicated 32-byte interface to a private 4-way set associative L2 cache. The
L2 interface runs at half processor speed, but transfers data twice per cycle to provide 19.2 GB/s of
bandwidth. RS64 IV internal data paths are 32 bytes wide. The RS64 IV processor also has a separate
16-byte system bus interface.
The RS64 IV has a total of five pipeline execution units. There is a Branch Unit, a Load/Store Unit, a
Fixed-point Unit, a Complex Fixed-point Unit and a Floating-point Unit. The processor has a 32-byte
interface to the dispatch logic. There is a current instruction stream dispatch buffer that is 16
instructions deep. The RS64 IV has an eight instruction deep branch buffer. The RS64 IV can sustain a
decode and execution rate of up to four instructions per cycle.
All of the arrays in the RS64 IV have either redundancy and ECC or parity and retry to support the
requirements for reliability, availability, and integrity. This enables full fault detection and correction
coverage.
SOI (silicon-on-insulator) technology reduces signal loss due to capacitance that normally occurs
along the silicon/conductor boundaries on the chip using a thin insulating boundary. This improves
signal-to-noise ratios within the chip and provides additional freedom in the layout of the circuit
design.