Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 9/30
9es3s1c1.doc
Rev 5.9
02/12/2003
Specifications
•
Center frequency of 180MHz
•
32K instruction and 32K data caches
•
Superscalar--up to 4 instructions per clock
•
Dynamic branch prediction
•
Multiple integer units
•
128-bit data bus
•
Separate L2 cache interface
•
128-bit L2 data bus
•
Fully JTAG compatible
Packaging
•
625 BGA
1.6. PowerPC RS64-II Processors
The PowerPC RS64-II is a 4-way, superscalar microprocessor implementing the 64-bit PowerPC
architecture. The internal structure of the processor is optimized for commercial transactions.
•
Full 64-bit implementation of the PowerPC architecture
•
Architectural extensions for 32-bit OS migration support
•
PowerPC Common Hardware Reference Platform (CHRP) compliant
•
4-way superscalar
•
On chip 64KB L1 Instruction cache and 64KB Data cache,128-byte line size
•
On chip L2 cache controller:
Up to 8 MB 4 way set associative L2 cache using 4 Mbit SRAM chips
Up to 32 MB 4 way set associative L2 cache using 16 Mbit SRAM chips
32 Byte Data Buses
•
PowerPC 6XX Bus Architecture:
16 Byte data bus (2:1, 3:1 or 4:1)
•
Full multiprocessor support
•
Technology:
CMOS 6S2
Standard Cell Library
•
Data Integrity:
L1 Data cache = ECC
L1 Instruction cache = Parity and Retry
L2 cache = ECC
Main Storage = ECC
I/O and Bus = Parity