Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 8/30
9es3s1c1.doc
Rev 5.9
02/12/2003
1.5.2. Cache and MMU Support
The PowerPC 620 microprocessor has separate 32-Kbyte, physically addressed instruction and data
caches. Both caches are 8-way set-associative. An on-chip 128-bit Level 2 cache interface provides
support for Level 2 caches of 1 Mbyte to 128 Mbytes in size, and is ECC protected.
The PowerPC 620 microprocessor also contains separate memory management units (MMUs) for
instructions and data. The MMUs support one Heptabyte (280) of virtual memory and one Terabyte
(240) of physical memory. Access privileges and memory protection are controlled on block or page
granularities. Address translation for recently accessed memory locations is provided by independent
64-entry, fully-associative, effective-to-real address translation caches. A large, 128-entry translation
lookaside buffer (TLB) provides efficient physical address translation and support for demand-paged
virtual memory management for both page- and variable-sized blocks.
1.5.3. Flexible Bus Support
The PowerPC 620 microprocessor has a high performance 128-bit data bus and a separate 40-bit
address bus. The interface protocol allows multiple masters to access system resources through a
central arbiter. Additionally, on-chip snooping logic maintains cache coherency in multiprocessor
applications.
1.5.4. PowerPC 620 Microprocessor Major Features
Technology
•
0.35-micron static CMOS technology
•
311 mm2
•
7.0 million transistors