Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 7/30
9es3s1c1.doc
Rev 5.9
02/12/2003
1.5. PowerPC 620 Processors
The PowerPC 620 microprocessor is a 64-bit implementation of the PowerPC® Reduced Instruction
Set Computer (RISC) architecture. The PowerPC 620 microprocessor provides high levels of
performance for technical and scientific work-stations, application and LAN servers and symmetric
multiprocessing computer systems and is software compatible with the PowerPC 601®, PowerPC
603®, and PowerPC 604® microprocessors.
It features a high bandwidth memory subsystem ideal for symmetric multiprocessing, transaction
processing and numerically intensive computing.
It is the 64-bit implementation of the PowerPC Architecture supporting both 32/64-bit applications.
1.5.1. 64-bit Advanced Superscalar Microprocessor
The PowerPC 620 microprocessor is a superscalar design capable of issuing four instructions per clock
cycle to six independent execution units, including:
•
two single-cycle integer units
•
multicycle integer unit
•
branch processing unit
•
load/store unit
•
floating-point unit
The PowerPC 620 microprocessor uses dynamic branch prediction to improve the accuracy of
instruction prefetching. Dynamic branch prediction, combined with the ability to speculatively execute
through four unresolved branches, minimizes pipeline stalls and allows the multiple execution units to
provide a high level of efficiency and throughput. The PowerPC 620 microprocessor supports out-of-
order execution with in-order instruction completion assuring precise exceptions.