Specifications

Escala Tower PL & S, E, T System Hardware
Chapter 1: Family Overview 6/30
9es3s1c1.doc
Rev 5.9
02/12/2003
1.4. PowerPC 604e Processors
The PowerPC 604e™ is a superscalar processor capable of issuing four instructions simultaneously.
As many as seven instructions can finish execution in parallel. The PowerPC 604e has six execution
units that can operate in parallel:
•
Floating-point unit (FPU)
•
Branch processing unit (BPU)
•
Load/store unit (LSU)
•
Three integer units (IUs):
Two single-cycle integer units (SCIUs)
One multiple-cycle integer unit (MCIU).
This parallel design, combined with the PowerPC architecture's specification of uniform instructions
that allows for rapid execution times, yields high efficiency and throughput. The PowerPC 604e
rename buffers, reservation stations, dynamic branch prediction, and completion unit increase
instruction throughput, guarantee in-order completion, and ensure a precise exception model. (Note
that the PowerPC architecture specification refers to all exceptions as interrupts.)
The PowerPC 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip
caches for instructions and data. The PowerPC 604e implements two 128-entry, two-way set (64-entry
per set) associative translation lookaside buffers (TLBs), one for instructions and one for data, and
provides support for demand-pages virtual memory address translation and variable-sized block
translation. The TLBs and the cache use least-recently-used (LRU) replacement algorithms.
The PowerPC 604e has a 64-bit external data bus and a 32-bit address bus. The PowerPC 604e
interface protocol allows multiple masters to compete for system resources through a central external
arbiter. Additionally, on-chip snooping logic maintains data cache coherency for multiprocessor
application. The PowerPC 604e supports single-beat and burst data transfers for memory accesses and
memory-mapped I/O accesses.
The PowerPC 604e uses an advanced, 3.3-V CMOS process technology and is fully compatible with
TTL devices.