Product manual

Managing Critical Data
77 A1 69UP Rev00 5-13
5.3.1.1 Parity
All data and control paths have parity generating and checking circuitry that verify
hardware integrity at the byte level.
5.3.1.2 ECC
The directors detect and correct single-bit and double-bit errors and report
uncorrectable 3-bit or more errors in cache.
5.3.1.3 LRC
The LRC calculation further assures data integrity. The check bytes are the XOR
(exclusive OR) of the accumulated bytes. Each record in memory also includes its
LRC byte, its physical memory address, and block number.
5.3.2 Disk Error Correction and Error Verification
The disk directors use idle time to read data and check the polynomial correction
bits for validity. If a disk read error occurs, the disk director reads all data on that
track to CDA 7 cache memory. The disk director writes several worst case patterns
to that track searching for media errors. When the test completes, the disk director
rewrites the data from cache to the disk device, verifying the write operation. The
disk microprocessor maps around any bad block (or blocks) detected during the
worst case write operation, thus skipping defects in the media. If necessary, the
disk microprocessor can reallocate up to 32 blocks of data on that track. To further
safeguard the data, each disk device has several spare cylinders available. If the
number of bad blocks per track exceeds 32 blocks, the disk director rewrites the
data to an available spare cylinder. This entire process is called “error
verification.”
The disk director increments a soft error counter with each bad block detected.
When the internal soft error threshold is reached, the CDA 7 service processor
automatically dials the Bull Competence Center and notifies the host system of
errors via sense data. This feature maximizes data availability by diagnosing
marginal media errors before data becomes unreadable.