Service manual

CHAPTER 3 THEORY OF OPERATION
3-2
1.2 Main PCB Block Diagram
Fig. 3-2 shows the block diagram of the main PCB.
Reset Circuit
Program + Font ROM
1MB, 4MB, 8MB
RAM
4MB, 8MB, 16MB
RAM (DIMM) (max. 128MB)
EEPROM
512 x 8 bit, 8192 x 8 bit
CPU Core
(SPARClite 133MHz)
A S I C
Oscillator 66.6MHz
Address Decoder
DRAM Control
Timer
FIFO
CDCC Parallel I/O
Soft Support
EEPROM I/O
Engine Control I/O
To Engine PCB
BUS
INT
To PC
USB I/O
To PC
Network Program
( MB)
PCI Bus Control
Scanner Controller
CCD unit
Oscillator 12MHz
Fig. 3-2