Service manual

CHAPTER 3 THEORY OF OPERATION
3-2
1.2 Main PCB Block Diagram
Fig. 3-2 shows the block diagram of the main PCB. (HL-5030/5040/5050/5070N)
Reset Circuit
Program + Font ROM
HL-5030:1MB
HL-5040:4MB
HL-5050/5070N:8MB
RAM
HL-5030:4MB
HL-5040:8MB
HL-5050/5070N:16MB
RAM (DIMM)
(max. 128MB)
Option for HL-5040/5050/5070N
EEPROM
HL-5030/5040/5050:512 x 8 bit
HL-5070N:8192 x 8 bit
CPU Core
(SPARClite 133MHz)
A S I C
Oscillator 66.6MHz
Address Decoder
DRAM Control
Timer
FIFO
CDCC Parallel I/O
(HL-5040/5050/5070N only)
Soft Support
EEPROM I/O
Engine Control I/O
To Engine PCB
BUS
INT
To PC
USB I/O
To PC
Network Program
(HL-5070N only)(1.5 MB)
STORAGE (0.5 MB)
PCI Bus Control
Network Controller
To PC
or Hub
(HL-5070N only)
Oscillator 12MHz
Oscillator 25MHz
(HL-5070N only)
Fig. 3-2