Datasheet

10
5V operation: Electrical Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T
A
=+25°C, V
DD1
= V
DD2
= +5.0V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Quiescent Supply Current 1 I
DD1
mA V
IN
= 0V
HCPL-9000/-0900 0.012 0.018
HCPL-9030/-0930 0.012 0.018
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 0.024 0.036
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 2.5 3.0
Quiescent Supply Current 2 I
DD2
mA V
IN
= 0V
HCPL-9000/-0900 5.0 6.0
HCPL-9030/-0930 5.0 6.0
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 8.0 12.0
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 6.0 9.0
Logic Input Current I
IN
-10 10 µA
Logic High Output Voltage V
OH
V
DD2
– 0.1 V
DD2
V I
OUT
= -20 µA, V
IN
= V
IH
0.8*V
DD2
V
DD2
– 0.5 V I
OUT
= -4 mA, V
IN
= V
IH
Logic Low Output Voltage V
OL
0 0.1 V I
OUT
= 20 µA, V
IN
= V
IL
0.5 0.8 V I
OUT
= 4 mA, V
IN
= V
IL
Switching Specications
Maximum Data Rate 100 110 MBd C
L
= 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic t
PHL
10 15 ns
Low Output
Propagation Delay Time to Logic t
PLH
10 15 ns
High Output
Pulse Width t
PW
10 ns
Pulse Width Distortion
[1]
|PWD| 2 3 ns
|t
PHL
– t
PLH
|
Propagation Delay Skew
[2]
t
PSK
4 6 ns
Output Rise Time (10 – 90%) t
R
1 3 ns
Output Fall Time (10 – 90%) t
F
1 3 ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance t
PHZ
3 5 ns
Low to High Impedance t
PLZ
3 5 ns
High Impedance to High t
PZH
3 5 ns
High Impedance to Low t
PZL
3 5 ns
Channel-to-Channel Skew t
CSK
2 3 ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CM
H
| 15 18 kV/µs V
cm
= 1000V
(Output Logic High or Logic Low)
[3]
|CM
L
|
Notes:
1. PWD is dened as |t
PHL
-t
PLH
|. %PWD is equal to the PWD divided by the pulse width.
2. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at 25°C.
3. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
OUT
> 0.8V
DD2
. CM
L
is the maximum common mode
input voltage that can be sustained while maintaining V
OUT
< 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.