Datasheet

ManualsBrandsBroadcom ManualsHigh Speed / Logic OptocouplersOptocoupler 110 MBit/s DIL-8

HCPL-9000/-0900, -9030/-0930,

HCPL-9031/-0931, -900J/-090J,

HCPL-901J/-091J, -902J/-092J

High Speed Digital Isolators

Data Sheet

Description

The HCPL-90xx and HCPL-09xx CMOS digital isolators

feature high speed performance and excellent transient

immunity specifications. The symmetric magnetic

coupling barrier gives these devices a typical pulse

width distortion of 2 ns, a typical propagation delay

skew of 4 ns and 100 Mbaud data rate, making them the

industry’s fastest digital isolators.

The single channel digital isolators (HCPL-9000/

-0900) features an active-low logic output enable.

The dual channel digital isolators are configured as

unidirectional (HCPL-9030/-0930) and bi-directional

(HCPL-9031/-0931), operating in full duplex mode making

it ideal for digital eldbus applications.

The quad channel digital isolators are configured as

unidirectional (HCPL-900J/-090J), two channels in one

direction and two channels in opposite direction (HCPL-

901J/-091J), and one channel in one direction and

three channels in opposite direction (HCPL-902J/-092J).

These high channel density make them ideally suited

to isolating data conversion devices, parallel buses and

peripheral interfaces.

They are available in 8-pin PDIP, 8-pin Gull Wing, 8-pin

SOIC packages, and 16–pin SOIC narrow-body and wide-

body packages. They are specied over the temperature

range of -40°C to +100°C.

CAUTION: It is advised that normal static precautions

be taken in handling and assembly of this component

to prevent damage and/or degradation, which may be

induced by ESD.

Features

• +3.3V and +5V TTL/CMOS compatible

• 3 ns max. pulse width distortion

•

6 ns max. propagation delay skew

• 15 ns max. propagation delay

• High speed: 100 MBd

• 15 kV/µs min. common mode rejection

• Tri-state output (HCPL-9000/-0900)

• 2500 V RMS isolation

• UL1577 and IEC 61010-1 approved

Applications

• Digital eldbus isolation

• Multiplexed data transmission

• Computer peripheral interface

• High speed digital systems

• Isolated data interfaces

• Logic level shifting

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Summary of content (14 pages)

PAGE 1
HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J High Speed Digital Isolators Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-90xx and HCPL-09xx CMOS digital isolators feature high speed performance and excellent transient immunity specifications.
PAGE 2
Selection Guide Device Number Channel Configuration Package HCPL-9000 Single 8-pin DIP (300 Mil) HCPL-0900 Single 8-pin Small Outline HCPL-9030 Dual 8-pin DIP (300 Mil) HCPL-0930 Dual 8-pin Small Outline HCPL-9031 Dual, Bi-Directional 8-pin DIP (300 Mil) HCPL-0931 Dual, Bi-Directional 8-pin Small Outline HCPL-900J Quad 16-pin Small Outline, Wide Body HCPL-090J Quad 16-pin Small Outline, Narrow Body HCPL-901J Quad, 2/2, Bi-Directional 16-pin Small Outline, Wide Body HCPL-091J Q
PAGE 3
Functional Diagrams Symbol Description Single Channel VDD1 Power Supply 1 VDD2 Power Supply 2 INX Logic Input Signal OUTX Logic Output Signal GND1 Power Supply Ground 1 GND2 Power Supply Ground 2 VOE Logic Output Enable (Single Channel), Active Low NC Not Connected VDD1 1 IN1 2 NC 3 GND1 4 Galvanic Isolation Pin Description 8 VDD2 7 VOE 6 OUT1 5 GND2 Truth Table IN1 VOE OUT1 L L L H L H L H Z H H Z HCPL-9000/0900 1 IN1 2 IN2 3 GND1 4 8 VDD2 V
PAGE 4
Package Outline Drawings HCPL-9000, HCPL-9030 and HCPL-9031 Standard DIP Packages 8 7 6 5 0.240 (6.096) 0.260 (6.604) 1 2 3 4 0.370 (9.398) 0.400 (10.160) 0.55 (1.397) 0.65 (1.651) 0.290 (7.366) 0.310 (7.874) 0.120 (3.048) 0.150 (3.810) 0.008 (0.203) 0.015 (0.381) 0.015 (0.381) 0.035 (0.889) 0.030 (0.762) 0.045 (1.143) 0.015 (0.380) 0.023 (0.584) 3° 8° 0.300 (7.620) 0.370 (9.398) 0.090 (2.286) 0.110 (2.794) 0.045 (1.143) 0.065 (1.
PAGE 5
HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package 0.189 (4.80) 0.197 (5.00) 8 7 6 5 0.228 (5.80) 0.244 (6.20) 0.150 (3.80) 0.157 (4.00) 1 2 3 4 0.013 (0.33) 0.020 (0.51) 0.010 (0.25) 0.020 (0.50) x 45° 0.008 (0.19) 0.010 (0.25) 0.004 (0.10) 0.010 (0.25) 0.054 (1.37) 0.069 (1.75) 0° 8° 0.040 (1.016) 0.060 (1.524) 0.016 (0.40) 0.050 (1.27) DIMENSIONS: INCHES (MILLIMETERS) MIN MAX HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package 0.397 (10.084) 0.413 (10.
PAGE 6
HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package 0.386 (9.802) 0.394 (9.999) 8 Pin 1 indent 1 0.228 (5.791) 0.244 (6.197) 0.152 (3.861) 0.157 (3.988) 0.013 (0.330) 0.020 (0.508) 0.054 (1.372) 0.068 (1.727) 0.010 (0.245) x 45° 0.020 (0.508) 0.008 (0.191) 0.010 (0.249) 0.050 (1.270) 0.060 (1.524) 0° – 8° TYP 0.040 (1.016) 0.060 (1.524) 0.016 (0.406) 0.050 (1.270) 0.004 (0.102) 0.010 (0.249) DIMENSIONS: INCHES (MILLIMETERS) MIN MAX Package Characteristics Parameter Symbol Min.
PAGE 7
Insulation and Safety Related Specifications Parameters Condition Min. Typ. Max. Units Barrier Impedance Single Channel Dual Channel Quad Channel Ω||pF >1014||3 >1014||3 >1014||7 Creepage Distance (External) 8-Pin PDIP 8-Pin SOIC 16-Pin SOIC Narrow Body 16-Pin SOIC Wide Body Leakage Current mm 7.036 4.026 4.026 8.077 240 VRMS 60 Hz 0.
PAGE 8
Absolute Maximum Ratings Parameters Symbol Min. Max. Units Storage Temperature TS –55 175 °C Ambient Operating Temperature [1] TA –55 125 °C Supply Voltage VDD1, VDD2 –0.5 7 V Input Voltage VIN –0.5 VDD1 +0.5 V Voltage Output Enable (HCPL-9000/-0900) VOE –0.5 VDD2 +0.5 V Output Voltage VOUT –0.5 VDD2 +0.5 V Output Current Drive IOUT 10 mA 260 °C Lead Solder Temperature (10s) ESD 2 kV Human Body Model Notes: 1.
PAGE 9
3.3V operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA=+25°C, VDD1 = 5V, VDD2 = 3.3 V. Parameter Symbol Min. Quiescent Supply Current 1 IDD1 HCPL-9000/-0900 HCPL-9030/-0930 HCPL-9031/-0931 HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J Quiescent Supply Current 2 0.008 0.008 1.5 0.018 3.3 1.5 Max.
PAGE 10
5V operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0 V. Parameter Symbol Min. Quiescent Supply Current 1 IDD1 HCPL-9000/-0900 HCPL-9030/-0930 HCPL-9031/-0931 HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J Quiescent Supply Current 2 0.012 0.012 2.5 0.024 5.0 2.5 Max. Logic Input Current IIN Logic High Output Voltage VOH 5.0 5.
PAGE 11
Mixed 5V/3.3V or 3.3V/5V operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0 V. Parameter Symbol Min. Quiescent Supply Current 1 IDD1 Typ. mA Max. VIN = 0V HCPL-9000/-0900 HCPL-9030/-0930 HCPL-9031/-0931 HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J 0.012 0.012 2.5 0.024 5.0 2.5 Quiescent Supply Current 2 0.018 0.018 3.0 0.
PAGE 12
Applications Information Bypassing and PC Board Layout Power Consumption The HCPL-90xx and HCPL-09xx digital isolators are extremely easy to use. No external interface circuitry is required because the isolators use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 1, the only external components required for proper operation are two 47 nF ceramic capacitors for decoupling the power supplies.
PAGE 13
Propagation Delay, Pulse Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit, which describes how quickly a logic signal propagates through a system as illustrated in Figure 3. 5 V CMOS INPUT VIN 50% 0V tPLH OUTPUT VOUT 90% 10% tPHL 90% 10% VOH 2.
PAGE 14
Propagation delay skew represents the uncertainty of where an edge might be after being sent through a digital isolator. Figure 5 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived.