Datasheet

8
Switching Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T
A
= +25°C, V
DD1
= V
DD2
= +5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Propagation Delay Time to Logic t
PHL
16 22 ns C
L
= 15 pF CMOS Signal Levels
Low Output
[3]
Propagation Delay Time to Logic t
PLH
16 22 ns C
L
= 15 pF CMOS Signal Levels
High Output
[3]
Pulse Width PW 20 ns C
L
= 15 pF CMOS Signal Levels
Maximum Data Rate 50 MBd C
L
= 15 pF CMOS Signal Levels
Pulse Width Distortion
[4]
|t
PHL
- t
PLH
| |PWD| 1 2 ns C
L
= 15 pF CMOS Signal Levels
Propagation Delay Skew
[5]
t
PSK
16 ns C
L
= 15 pF CMOS Signal Levels
Output Rise Time (10% – 90%) t
R
8 ns C
L
= 15 pF CMOS Signal Levels
Output Fall Time (90% - 10%) t
F
6 ns C
L
= 15 pF CMOS Signal Levels
Common Mode Transient Immunity |CM
H
| 10 15 kV/µs V
CM
= 1000 V
,
T
A
= 25°C,
at Logic High Output
[6]
V
I
= V
DD1,
V
O
> 0.8 V
DD2
Common Mode Transient Immunity |CM
L
| 10 15 kV/µs V
CM
= 1000 V
,
T
A
= 25°C,
at Logic Low Output
[6]
V
I
= 0 V
,
V
O
< 0.8 V