Datasheet

ManualsBrandsBROADCOM ManualsOptoelectronics & DisplaysHigh-speed Digital-CMOS-Logic-Gate Optocoupler DIP 8 Type (misc.) 12.5 MBd, CMOS, 8 ns

Features

• +5 V CMOS compatibility

• 8 ns maximum pulse width distortion

• 20 ns maximum prop. delay skew

• High speed: 12 Mbd

• 40 ns maximum prop. delay

• 10 kV/µs minimum common mode rejection

• -40°C to 100°C temperature range

• Safety and regulatory approvals

UL Recognized

3750 V rms for 1 min. per UL 1577

5000 V rms for 1 min. per UL 1577 (for HCPL-7710

option 020)

CSA Component Acceptance Notice #5

IEC/EN/DIN EN 60747-5-2

– V

IORM

= 630 Vpeak for HCPL-7710 Option 060

– V

IORM

= 560 Vpeak for HCPL-0710 Option 060

Applications

• Digital eldbus isolation: DeviceNet, SDS, Probus

• AC plasma display panel level shifting

• Multiplexed data transmission

• Computer peripheral interface

• Microprocessor system interface

Description

Available in either an 8-pin DIP or SO-8 package style

respectively, the HCPL-7710 or HCPL-0710 optocouplers

utilize the latest CMOS IC technology to achieve outstand-

ing performance with very low power consumption. The

HCPL-x710 require only two bypass capacitors for complete

CMOS compatibility.

Basic building blocks of the HCPL-x710 are a CMOS LED

driver IC, a high speed LED and a CMOS detector IC. A

CMOS logic input signal controls the LED driver IC which

supplies current to the LED. The detector IC incorporates

an integrated photodiode, a high-speed transimped-

ance amplier, and a voltage comparator with an output

driver.

Functional Diagram

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

* Pin 3 is the anode of the internal LED and must be left

unconnected for guaranteed data sheet performance.

Pin 7 is not connected internally.

** A 0.1 µF bypass capacitor must be connected

between pins 1 and 4, and 5 and 8.

HCPL-7710/0710

40 ns Propagation Delay, CMOS Optocoupler

Data Sheet

SHIELD

**V

DD1

NC*

GND

DD2

GND

, INPUT LED1

OFF

TRUTH TABLE

(POSITIVE LOGIC)

NC*

LED1

, OUTPUT

SHIELD

**V

DD1

NC*

GND

DD2

GND

, INPUT LED1

OFF

TRUTH TABLE

(POSITIVE LOGIC)

NC*

LED1

, OUTPUT

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Summary of content (18 pages)

PAGE 1
HCPL-7710/0710 40 ns Propagation Delay, CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Available in either an 8-pin DIP or SO-8 package style respectively, the HCPL-7710 or HCPL-0710 optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-x710 require only two bypass capacitors for complete CMOS compatibility.
PAGE 2
Selection Guide 8-Pin DIP (300 Mil) HCPL-7710 Small Outline SO-8 HCPL-0710 Ordering Information HCPL-0710 and HCPL-7710 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
PAGE 3
Package Outline Drawing HCPL-7710 8-Pin DIP Package 7.62 ± 0.25 (0.300 ± 0.010) 9.65 ± 0.25 (0.380 ± 0.010) 8 TYPE NUMBER 7 6 5 6.35 ± 0.25 (0.250 ± 0.010) DATE CODE A XXXX YYWW 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5° TYP. 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) DIMENSIONS IN MILLIMETERS AND (INCHES).
PAGE 4
Package Outline Drawing HCPL-0710 Outline Drawing (Small Outline SO-8 Package) LAND PATTERN RECOMMENDATION 8 7 6 5 5.994 ± 0.203 (0.236 ± 0.008) XXXV YWW 3.937 ± 0.127 (0.155 ± 0.005) TYPE NUMBER (LAST 3 DIGITS) 7.49 (0.295) DATE CODE PIN ONE 1 2 3 4 1.9 (0.075) 0.406 ± 0.076 (0.016 ± 0.003) 1.270 BSC (0.050) 0.64 (0.025) * 5.080 ± 0.127 (0.200 ± 0.005) 7° 3.175 ± 0.127 (0.125 ± 0.005) 1.524 (0.060) 45° X 0.432 (0.017) 0 ~ 7° 0.228 ± 0.025 (0.009 ± 0.001) 0.203 ± 0.102 (0.008 ± 0.
PAGE 5
Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax 260 +0/-5 °C TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 217 °C RAMP-UP 3 °C/SEC. MAX. 150 - 200 °C RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL 60 to 150 SEC. t 25 °C to PEAK TIME NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C Note: Non-halide flux should be used.
PAGE 6
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060) Description Symbol Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤150 V rms for rated mains voltage ≤300 V rms for rated mains voltage ≤450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage VIORM Input to Output Test Voltage, Method b† VPR VIORM x 1.
PAGE 7
Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V. DC Specifications Parameter Symbol Logic Low Input Supply Current [1] Typ. Max. Units Test Conditions IDD1L 6.0 10.0 mA VI = 0 V Logic High Input Supply Current IDD1H 1.5 3.0 mA VI = VDDI Input Supply Current IDD1 13.0 mA Output Supply Current IDD2 11.
PAGE 8
Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage [8, 9, 10] 0710 VISO Typ. Max. 3750 7710 3750 Option 020 5000 Units Test Conditions Vrms RH = 50%, t = 1 min., TA = 25°C Resistance (Input-Output) [8] RI-O 1012 W VI-O = 500 Vdc Capacitance (Input-Output) [8] CI-O 0.6 pF f = 1 MHz Input Capacitance [11] CI 3.
PAGE 9
4 7 15 6 3 2 TF (ns) TR (ns) PWD (ns) 14 4 13 1 0 3 0 20 40 60 12 80 0 20 40 TA (C) 60 2 80 6 27 5 25 TPLH 23 21 19 3 2 15 15 20 25 30 35 40 45 0 50 17 15 13 11 9 1 17 7 15 20 25 30 35 40 45 5 50 0 5 10 C I (pF) CI (pF) Figure 7. Typical propagation delays vs. output load capacitance. 80 25 TR (ns) PWD (ns) TPHL 60 HCPL-0710 fig 6 4 19 40 Figure 6. Typical fall time vs. temperature. HCPL-0710 fig 5 29 21 20 TA (C) Figure 5.
PAGE 10
Application Information Bypassing and PC Board Layout The HCPL-x710 optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-x710 use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 12, the only external components VDD1 VDD2 8 1 required for proper operation are two bypass capacitors. Capacitor values should be between 0.01 µF and 0.1 µF.
PAGE 11
Pulse-width distortion (PWD) is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 - 30% of the minimum pulse width is tolerable. The PWD specification for the HCPL-x710 is 8 ns (10%) maximum across recommended operating conditions.
PAGE 12
Digital Field Bus Communication Networks To date, despite its many drawbacks, the 4 - 20 mA analog current loop has been the most widely accepted standard for implementing process control systems. In today’s manufacturing environment, however, automated systems are expected to help manage the process, not merely monitor it. With the advent of digital field bus communication networks such as DeviceNet, PROFIBUS, and Smart Distributed Systems (SDS), gone are the days of constrained information.
PAGE 13
AC LINE NODE/APP SPECIFIC uP/CAN HCPL x710 LOCAL NODE SUPPLY GALVANIC ISOLATION BOUNDARY HCPL x710 5 V REG. TRANSCEIVER DRAIN/SHIELD V+ (SIGNAL) V– (SIGNAL) V+ (POWER) V– (POWER) SIGNAL POWER NETWORK POWER SUPPLY Figure 18. Typical DeviceNet node.
PAGE 14
Isolated Node with Transceiver Powered by the Network Figure 20 shows a node powered by both the network and another source. In this case, the transceiver and isolated (network) side of the two optocouplers are powered by the network. The rest of the node is powered by the AC line which is very beneficial when an application requires a significant amount of power. This method is also desirable as it does not heavily load the network.
PAGE 15
Isolated Node Providing Power to the Network Figure 21 shows a node providing power to the network. The AC line powers a regulator which provides five (5) volts locally. The AC line also powers a 24 volt isolated supply, which powers the network, and another five-volt regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers.
PAGE 16
Power Supplies and Bypassing The recommended DeviceNet application circuit is shown in Figure 22. Since the HCPL-x710 are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the CAN transceiver. Two bypass capacitors (with values between 0.01 and 0.1 µF) are required and should be located as close as possible to GALVANIC ISOLATION BOUNDARY ISO 5 V 1 VDD1 TX0 2 VIN 0.01 µF 3 5V VDD2 8 + 0.01 µF 7 HCPL-0710 TxD VO 6 4 GND1 GND2 5 5 V+ + C4 0.
PAGE 17
Power Supplies and Bypassing The recommended PROFIBUS application circuit is shown in Figure 24. Since the HCPL-x710 are fully compatible with CMOS logic level signals, the optocoup ler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 and 0.1 µF) are required and should be located as close as possible to the input and output power-supply pins of the HCPLx710.
PAGE 18
For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.