Datasheet
Figure 31. Not recommended open collector drive circuit.
Figure 32. Recommended LED drive circuit for ultra-high CMR.
Figure 33. Under voltage lock out.
Under Voltage Lockout Feature
The HCPL-3180 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the HCPL-3180 supply voltage
(equivalent to the fully charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low
resistance state. When the HCPL-3180 output is in the
high state and the supply voltage drops below the HCPL-
3180 V
UVLO-
threshold (typ 7.5 V) the optocoupler output
will go into the low state. When the HCPL-3180 output is
in the low state and the supply voltage rises above the
HCPL-3180 V
UVLO+
threshold (typ 8.5 V) the optocoupler
output will go into the high state (assume LED is “ON”).
IPM Dead Time and Propagation Delay Specications
The HCPL-3180 includes a Propagation Delay Dierence
(PDD) specication intended to help designers minimize
“dead time” in their power inverter designs. Dead time is
the time during which the high and low side power tran-
sistors are o. Any overlap in Q1 and Q2 conduction will
result in large currents owing through the power devices
from the high voltage to the low-voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn o of LED1)
so that under worst-case conditions, transistor Q1 has
just turned o when transistor Q2 turns on, as shown in
Figure 34. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propa-
gation delay dierence specication, PDD
MAX
, which is
specied to be 90 ns over the operating temperature
range of -40 °C to +100 °C.
Figure 34. Minimum LED skew for zero dead time.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
V
O
– OUTPUT VOLTAGE – V
0
0
(V
CC
- V
EE
) – SUPPLY VOLTAGE – V
10
5
20
14
16
18
10 15
2
20
6
8
4
12
t
PHL MAX
t
PLH MIN
PDD* MAX = (t
PHL
-
t
PLH
)
MAX
= t
PHL MAX
-
t
PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS, THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON