Datasheet

11
3.0 V
V
OL
INPUT
V
E
OUTPUT
V
O
t
PZL
t
PLZ
1.3 V
0 V
V
OH
1.5 V
OUTPUT
V
O
S1 OPEN
S2 CLOSED
S1 CLOSED
S2 OPEN
t
PZH
t
PHZ
1.3 V
0 V
0.5 V
S1 AND
S2 CLOSED
0.5 V
S1 AND
S2 CLOSED
1.3 V
7
1
4
5
6
8
HCPL-2200
GND
V
CC
+5 V
619
INPUT V
C
MONITORING
NODE
PULSE
GENERATOR
Z
O
= 50
t
r
= t
f
=
5 ns
C
L
C
L
= 15 pF INCLUDING PROBE
AND JIG CAPACITANCES
.
V
O
V
CC
D
1
D
2
5 k
D
3
D
4
2
3
D
1-4
ARE 1N916 OR 1N3064.
I
F
S1
S2
Figure 10. Typical rise, fall time vs.
temperature.
Figure 8. Typical logic low enable
propagation delay vs. temperature.
Figure 9. Typical logic high enable
propagation delay vs. temperature.
Figure 7. Test circuit for t
PHZ
, t
PZH
, t
PLZ
, and t
PZL
.
Figure 6. Typical propagation delays vs.
temperature.
T
p
– ENABLE PROPAGATION DELAY – ns
-60
0
T
A
– TEMPERATURE – °C
100
100
-20
40
20 60-40 0 40 80
60
80
20
t
PLZ
C
L
= 15 pF
t
PZL
V
CC
20 V
4.5 V
20 V
4.5 V
t
P
– ENABLE PROPAGATION DELAY – ns
-60
0
T
A
– TEMPERATURE – °C
100
150
200
-20
50
20 60-40 0 40 80
100
C
L
= 15 pF
20 V
V
CC
t
PHZ
t
PZH
20 V
4.5 V
4.5 V
t
P
– PROPAGATION DELAY – ns
-60
50
T
A
– TEMPERATURE – °C
100
200
250
-20
100
20 60-40 0 40 80
150
I
F
(mA)
5
3
1.6
1.6
3
5
t
PLH
t
PHL
V
CC
= 5 V
C1 (120 pF) PEAKING
CAPACITOR IS USED.
SEE FIGURE 5.
t
r
,
t
f
– RISE, FALL TIME – ns
-60
0
T
A
– TEMPERATURE – °C
100
120
-20
40
20 60-40 0 40 80
80
100
20
V
CC
= 5 V
C
2
= 15 pF
t
r
60
t
f