Datasheet

23
Under Voltage Lockout Feature. (Discussion applies to
HCPL-3120, HCPL-J312, and HCNW3120)
The HCPL-3120 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the HCPL-3120 supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low re-
sistance state. When the HCPL-3120 output is in the high
state and the supply voltage drops below the HCPL-
3120 V
UVLO–
threshold (9.5 < V
UVLO–
< 12.0) the opto-
coupler output will go into the low state with a typical
delay, UVLO Turn O Delay, of 0.6 µs.
When the HCPL-3120 output is in the low state and
the supply voltage rises above the HCPL-3120 V
UVLO+
threshold (11.0 < V
UVLO+
< 13.5) the optocoupler output
will go into the high state (assumes LED is “ON”) with a
typical delay, UVLO Turn On Delay of 0.8 µs.
IPM Dead Time and Propagation Delay Specications.
(Discussion applies to HCPL-3120, HCPL-J312, and
HCNW3120)
The HCPL-3120 includes a Propagation Delay Dierence
(PDD) specication intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 25) are o.
Any overlap in Q1 and Q2 conduction will result in large
currents owing through the power devices between
the high and low voltage motor rails.
Figure 35. Minimum LED skew for zero dead time.
Figure 36. Waveforms for dead time.
t
PHL MAX
t
PLH MIN
PDD* MAX = (t
PHL
- t
PLH
)
MAX
= t
PHL MAX
- t
PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
HCPL-3120 fig 35
t
PLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
- t
PHL MIN
) + (t
PLH MAX
- t
PLH MIN
)
= (t
PHL MAX
- t
PLH MIN
) – (t
PHL MIN
- t
PLH MAX
)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
HCPL-3120 fig 36
t
PHL MIN
t
PHL MAX
t
PLH MAX
PDD* MAX
(t
PHL-
t
PLH
)
MAX