Datasheet

22
CMR with the LED On (CMR
H
).
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriv-
ing the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient.
A minimum LED current of 10 mA provides adequate
margin over the maximum I
FLH
of 5 mA to achieve 25 kV/
µs CMR.
CMR with the LED O (CMR
L
).
A high CMR LED drive circuit must keep the LED o
(V
F
≤ V
F(OFF)
) during common mode transients. For
example, during a -dV
cm
/dt transient in Figure 31, the
current owing through C
LEDP
also ows through the
HCPL-3120 fig 31
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–
V
CC
= 18 V
• • •
• • •
0.1
µF
+
–
–
Figure 33. Recommended LED drive circuit for ultra-high CMR.
HCPL-3120 fig 33
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Figure 31. Equivalent circuit for gure 25 during common mode transient. Figure 32. Not recommended open collector drive circuit.
HCPL-3120 fig 32
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
R
SAT
and V
SAT
of the logic gate. As long as the low state
voltage developed across the logic gate is less than
V
F(OFF)
, the LED will remain o and no common mode
failure will occur.
The open collector drive circuit, shown in Figure 32,
cannot keep the LED o during a +dVcm/dt transient,
since all the current owing through C
LEDN
must be
supplied by the LED, and it is not recommended for
applica-tions requiring ultra high CMR
L
performance.
Figure 33 is an alternative drive circuit which, like the rec-
ommended applica-tion circuit (Figure 25), does achieve
ultra high CMR performance by shunting the LED in the
o state.
Figure 34. Under voltage lock out.
V
O
– OUTPUT VOLTAGE – V
0
0
(V
CC
- V
EE
) – SUPPLY VOLTAGE – V
10
5
HCPL-3120 fig 34
14
10 15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1)
(12.3, 0.1)