Datasheet

18
Applications Information
Eliminating Negative IGBT Gate Drive (Discussion applies
to HCPL-3120, HCPL-J312, and HCNW3120)
To keep the IGBT rmly o, the HCPL-3120 has a very
low maximum V
OL
specication of 0.5 V. The HCPL-3120
realizes this very low V
OL
by using a DMOS transistor
with 1 Ω (typical) on resistance in its pull down circuit.
When the HCPL-3120 is in the low state, the IGBT gate
is shorted to the emitter by Rg + 1 Ω. Minimizing Rg
and the lead inductance from the HCPL-3120 to the
IGBT gate and emitter (possibly by mounting the HCPL-
Figure 25. Recommended LED drive and application circuit.
+ HVDC
3-PHASE
AC
- HVDC
HCPL-3120 fig 25
0.1 µF
V
CC
= 18 V
1
3
+
–
2
4
8
6
7
5
270 Ω
HCPL-3120
+5 V
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
3120 on a small PC board directly above the IGBT) can
eliminate the need for negative IGBT gate drive in many
applications as shown in Figure 25. Care should be taken
with such a PC board design to avoid routing the IGBT
collector or emitter traces close to the HCPL-3120 input
as this can result in unwanted coupling of transient
signals into the HCPL-3120 and degrade performance. (If
the IGBT drain must be routed near the HCPL-3120 input,
then the LED should be reverse-biased when in the o
state, to prevent the transient signals coupled from the
IGBT drain from turning on the HCPL-3120.)