Datasheet

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AV02-1077EN - March 11, 2008

Appendix B: Application circuit

Figure B1. Application circuit for APDS-9300

The power supply lines must be decoupled with a 0.1 uF

capacitor placed as close to the device package as pos-

sible, as shown in Figure B1. The bypass capacitor should

have low eective series resistance (ESR) and low eec-

tive series inductance (ESI), such as the common ceramic

types, which provide a low impedance path to ground at

high frequencies to handle transient currents caused by

internal logic switching.

Pull-up resistors, R1 and R2, maintain the SDA and SCL

lines at a high level when the bus is free and ensure the

signals are pulled up from a low to a high level within the

required rise time. For a complete description of I

C maxi-

mum and minimum R1 and R2 values, please review the

C Specication at http://www.semiconductors.philips.

com.

A pull-up resistor, R3, is also required for the interrupt

(INT), which functions as a wired-AND signal in a similar

fashion to the SCL and SDA lines. A typical impedance

value between 10 kΩ and 100 kΩ can be used.

APDS-9300

Pin 1: V

Pin 5

Pin 4

Pin 6

Pin 2: GND

0.1uF

Pin 3

** ADDR_SEL

INT

SDA

SCL

Pin 1

Pin 2

MCU

** Note:

ADDR_SEL Float : Slave address is 0111001