Datasheet

8
Notes:
1. Derate linearly above 85 °C free-air temperature at a rate of 0.3 mA/ °C.
2. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with I
O
peak minimum = 2.0 A. See applications
section for additional details on limiting I
OH
peak.
3. Derate linearly above 85 °C free-air temperature at a rate of 12.5 mW/ °C .
4. Derate linearly above 85 °C free-air temperature at a rate of 13.75 mW/ °C. The maximum LED junction temperature should not exceed 125 °C.
5. Maximum pulse width = 10 µs.
6. Output is sourced at -2.0 A/2.0 A with a maximum pulse width = 10 µs.
7. In this test V
OH
is measured with a dc load current. When driving capacitive loads, V
OH
will approach V
CC
as I
OH
approaches zero amps.
8. Maximum pulse width = 1 ms.
9. Pulse Width Distortion (PWD) is dened as |t
PHL
-t
PLH
| for any given device.
10. The dierence between t
PHL
and t
PLH
between any two ACPL-P346 parts under the same test condition.
11. t
PSK
is equal to the worst case di erence in t
PHL
and/or t
PLH
that will be seen between units at any given temperature and specied test conditions.
12. Pin 2 needs to be connected to LED common. Split resistor network in the ratio 1.5:1 with 232 Ω at the anode and 154 Ω at the cathode.
13. Common mode transient immunity in the high state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the output
will remain in the high state (i.e., V
O
> 10.0 V).
14. Common mode transient immunity in a low state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the output
will remain in a low state (i.e., V
O
< 1.0 V).
15. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V
RMS
for 1 second (leakage detection
current limit, I
I-O
≤ 5 µA).
16. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V
RMS
for 1 second (leakage detection
current limit, I
I-O
≤ 5 µA).
17. Device considered a two-terminal device: pins 1, 2, and 3 shorted together and pins 4, 5 and 6 shorted together.
18. The device was mounted on a high conductivity test board as per JEDEC 51-7.