Datasheet

15
Table 8. Common Mode Pulse Polarity and LED current Transients
dV
CM
/dt I
LP
Direction I
LP
Direction
If |I
LP
| < |I
LN
|,
I
F
is momentarily
If |I
LP
| > |I
LN
|,
I
F
is momentarily
Positive (>0) Away from LED anode through C
LA
Away from LED cathode through C
LC
Increase Decrease
Negative(<0) Toward LED anode through C
LA
Toward LED cathode through C
LC
Decrease Increase
t
PHL MAX
t
PLH MIN
PDD* MAX = (t
PHL
- t
PLH
) MAX = t
PHL MAX
- t
PLH MIN
*PDD = Propagation Delay Dierence
Note: for PDD calculations the propagation delays
Are taken at the same temperature and test conditions.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PLH MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
- t
PHL MIN
) + (t
PLH MAX
- t
PLH MIN
)
= (t
PHL MAX
- t
PLH MIN
) + (t
PHL MIN
- t
PLH MAX
)
= PDD* MAX - PDD* MIN
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PLH MIN
t
PHL MAX
t
PLH MAX
PDD* MAX
*PDD = Propagation Delay Dierence
Note: For Dead Time and PDD calculations all propagation
delays are taken at the same temperature and test conditions.
V
OUT1
I
LED2
V
OUT2
I
LED1
(t
PHL
- t
PLH
)
MAX
Figure 24. Minimum LED skew for zero dead time
Figure 25. Waveforms for dead time
Dead Time and Propagation Delay Specications
The ACPL-P346/W346 includes a Propagation Delay Dier-
ence (PDD) specication intended to help designers mini-
mize “dead time” in their power inverter designs. Dead
time is the time period during which both the high and
low side power transistors (Q1 and Q2 in Figure 22) are o.
Any overlap in Q1 and Q2 conduction will result in large
currents owing through the power devices between the
high and low voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn o of LED1)
so that under worst-case conditions, transistor Q1 has just
turned o when transistor Q2 turns on, as shown in Figure
24. The amount of delay necessary to achieve this condi-
tion is equal to the maximum value of the propagation
delay dierence specication, PDD
MAX
, which is specied
to be 100 ns over the operating temperature range of 40
°C to 105 °C.
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the dierence between the maximum and minimum
propagation delay dierence specications as shown in
Figure 25. The maximum dead time for the ACPL-P346/
W346 is 100 ns (= 50 ns - (-50 ns)) over an operating tem-
perature range of -40 °C to 105 °C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical MOSFETs.
LED Current Input with Hysteresis
The detector has optical receiver input stage with built in
Schmitt trigger to provide logic compatible waveforms,
eliminating the need for additional wave shaping. The
hysteresis (Figure 12) provides dierential mode noise
immunity and minimizes the potential for output signal
chatter.