Datasheet

13
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Data subject to change. Copyright © 2007 Avago Technologies, Limited. All rights reserved. Obsoletes AV01-0634EN
AV02-0158EN - April 19, 2007
Dead Time and Propagation Delay Specications
The ACPL-P314/W314 includes a Propagation Delay Dif-
ference (PDD) specication intended to help designers
minimize dead time” in their power inverter designs.
Dead time is the time high and low side power transistors
are o. Any overlap in Ql and Q2 conduction will result
in large currents owing through the power devices
from the high voltage to the low-voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn o of LED1)
so that under worst-case conditions, transistor Q1 has
just turned o when transistor Q2 turns on, as shown in
Figure 26. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propa-
gation delay dierence specication, PDD max, which is
specied to be 500 ns over the operating temperature
range of -40° to 100°C.
Figure 26. Minimum LED Skew for Zero Dead Time.
Figure 27. Waveforms for Dead Time.
Figure 25. Recommended LED Drive Circuit for Ultra-High CMR Dead Time and Propaga-
tion Delay Specications.
C
LEDP
C
LEDN
61
52
43
SHIELD
+5 V
C
LEDP
C
LEDN
61
52
43
+5 V
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the dierence between the maximum and minimum
propagation delay dierence specication as shown in
Figure 27. The maximum dead time for the ACPL-P314/
W314 is 1 µs (= 0.5 µs - (-0.5 µs)) over the operating tem-
perature range of –40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other
and are switching identical IGBTs.