Datasheet

8
Switching Specications (AC)
Over recommended temperature (T
A
= -40° C to +105° C), supply voltage (2.7 V ≤ V
DD
≤ 5.5 V). All typical specications
are at V
DD
= 2.7 V, T
A
= 25° C
Parameter Symbol Min Typ Max Units Test Conditions
Propagation Delay Time
to Logic Low Output
[1]
t
PHL
130 250 ns I
F
=2.2mA, C
L
=15pF (Figure 8, 12)
CMOS Signal Levels
Propagation Delay Time
to Logic High Output
[1]
t
PLH
115 250 ns I
F
=2.2mA, C
L
=15pF (Figure 9, 12)
CMOS Signal Levels
Pulse Width Distortion
[2]
PWD 200 ns CMOS Signal Levels
Propagation Delay Skew
[3]
t
PSK
220 ns
Output Rise Time
(10% – 90%)
t
R
11 ns I
F
= 2.2 mA, C
L
= 15 pF,
CMOS Signal Levels.
Output Fall Time
(90% – 10%)
t
F
11 ns I
F
= 2.2 mA, C
L
= 15 pF,
CMOS Signal Levels.
Static Common Mode
Transient Immunity at
Logic High Output
[4]
|CM
H
| 25 40
kV/μs
V
CM
= 1000 V, T
A
= 25° C,
I
F
= 2.2 mA, C
L
= 15 pF, V
I
= 5 V
(R
T
= 1.6 kW) or V
I
= 3.3 V
(R
T
= 840 W)
CMOS Signal Levels
Figure 13
Static Common Mode
Transient Immunity at
Logic Low Output
[5]
|CM
L
| 25 40
kV/μs
V
CM
= 1000 V, T
A
= 25° C,
I
F
= 0 mA, C
L
= 15 pF, V
I
= 0 V
(R
T
= 1.6 kW) or (R
T
= 840 W)
CMOS Signal Levels
Figure 13
Notes:
1. t
PHL
propagation delay is measured from the 50% (V
in
or I
F
) on the falling edge of the input pulse to the 50% V
DD
of the falling edge of the V
O
signal.
t
PLH
propagation delay is measured from the 50% (V
in
or I
F
) on the rising edge of the input pulse to the 50% level of the rising edge of the V
O
signal
2. PWD is dened as |t
PHL
- t
PLH
|
3. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within the
recommended operating conditions.
4. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CM
L
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state.
6. Use of a 0.1 μF bypass capacitor connected between Vdd and ground is recommended.
Package Characteristics
All typical at T
A
= 25° C
Parameter Symbol Part Number Min Typ Max Units Test Conditions
Input-Output Insulation V
ISO
ACPL-M21L
/024L/021L
3750 V
rms
RH < 50% for 1 min.
T
A
= 25° C
ACPL-W21L
/K24L
5000
Input-Output Resistance R
I-O
10
12
W
V
I-O
= 500 V
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz, T
A
= 25° C