Datasheet

11
Figure 12. Circuit for t
PLH
, t
PHL
, t
r
, t
f
* 0.1 µF BYPASS — SEE NOTE 6 above.
[6]
PULSE GEN
t
r
= t
f
= 11 ns
f = 1.0 MHz
50% DUTY
CYCLE
Vdd
*
OUTPUT V
O
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
C
L
= 15 pF
I
F
PULSE GEN
t
r
= t
f
= 11 ns
f = 1.0 MHz
50% DUTY
CYCLE
Vdd
OUTPUT V
O
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
C
L
= 15 pF
I
F
PULSE GEN
t
r
= t
f
= 11 ns
f = 1.0 MHz
50% DUTY
CYCLE
*
Vdd
OUTPUT V
O
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
C
L
= 15 pF
I
F
ACPL-M21L
ACPL-021L
ACPL-024L/K24L
INPUT I
F
OUTPUT V
O
I
F
(ON)
0 mA
50% I
F
(ON)
V
OH
V
OL
50%
t
PLH
t
PHL
6
4
Shield
1
3
5
4
1
Shield
3
2
5
8
6
7
2
3
8
5
6
Shield
1
4
7
*
PULSE GEN
t
r
= t
f
= 11 ns
f = 1.0 MHz
50% DUTY
CYCLE
Vdd
*
OUTPUT V
O
MONITORING
NODE
Rm
INPUT
MONITORING
NODE
C
L
= 15 pF
I
F
ACPL-W21L
6
4
Shield
1
3
5
2