Datasheet

11
Figure 19. Typical application circuit.
Denitions
Gain
Gain is dened as the slope of the best-t line of dieren-
tial output voltage (V
OUT+
– V
OUT-
) over the nominal input
range, with oset error adjusted out.
Nonlinearity
Nonlinearity is dened as half of the peak-to-peak output
deviation from the best-t gain line, expressed as a per-
centage of the full-scale dierential output voltage.
Common Mode Transient Immunity, CMTI, also known
as Common Mode Rejection
CMTI is tested by applying an exponentially rising/falling
voltage step on pin 4 (GND1) with respect to pin 5 (GND2).
The rise time of the test waveform is set to approximately
50 ns. The amplitude of the step is adjusted until the dif-
ferential output (V
OUT+
– V
OUT-
) exhibits more than a 200
mV deviation from the average output voltage for more
than 1µs. The ACPL-C87x will continue to function if more
than 10 kV/ms common mode slopes are applied, as long
as the breakdown voltage limitations are observed.
Power Supply Rejection, PSR
PSRR is the ratio of dierential amplitude of the ripple
outputs over power supply ripple voltage, referred to the
input, expressed in dB.
Application Information
Application Circuit
The typical application circuit is shown in Figure 19.
The ACPL-C87X voltage sensor is often used in photo-
voltaic (PV) panel voltage measurement and tracking in
PV inverters, and DC bus voltage monitoring in motor
drivers. The high voltage across rails needs to be scaled
down to t the input range of the iso-amp by choosing R1
and R2 values according to appropriate ratio.
The ACPL-C87X senses the single-ended input signal
and produces dierential outputs across the galvanic
isolation barrier. The dierential outputs (Vout+, Vout-)
can be connected to an op-amp to convert to a single-
ended signal or directly to two ADCs. The op-amp used in
the external post-amplier circuit should be of suciently
high precision so that it does not contribute a signicant
amount of oset or oset drift relative to the contribu-
tion from the isolation amplier. Generally, op-amps with
bipolar input stages exhibit better oset performance
than op-amps with JFET or MOSFET input stages.
In addition, the op-amp should also have enough
bandwidth and slew rate so that it does not adversely
aect the response speed of the overall circuit. The post-
amplier circuit includes a pair of capacitors (C4 and C5)
that form a single-pole low-pass lter; these capacitors
allow the bandwidth of the post-amp to be adjusted in-
dependently of the gain and are useful for reducing the
output noise from the isolation amplier.
The gain-setting resistors in the post-amp should have a
tolerance of 1% or better to ensure adequate CMRR and
adequate gain tolerance for the overall circuit. Resistor
networks can be used that have much better ratio toler-
ances than can be achieved using discrete resistors. A
resistor network also reduces the total number of compo-
nents for the circuit as well as the required board space.
V
DD1
1
V
IN
2
SHDN3
GND14 GND2 5
V
OUT-
6
V
OUT+
7
V
DD2
8
U1
ACPL-C87X
GND2
R4
10K,1%
GND2
V
DD2
V
DD1
Vout
GND1
L1
L2
R2
10K
C1
100 pF
C2
100 nF
C3
100 nF
R3
10K,1%
R1
U2
OPA237
V+
V-
C4
100 pF
R5
10K, 1%
C5
100 pF
R6
10K, 1%