Datasheet

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ACPL-772L and ACPL-072L

3.3V/5V High Speed CMOS Optocoupler

Data Sheet

* Pin 3 is the anode of the internal LED and must be left unconnected

for guaranteed datasheet performance. Pin 7 is not connected

internally.

** A 0.1uF bypass capacitor must be connected between pins 1 and 4,

and 5 and 8.

TRUTH TABLE (POSITIVE LOGIC)

, INPUT LED1 V

, OUTPUT

H OFF H

L ON L

Description

Available in either an 8-pin DIP or SO-8 style respectively,

the ACPL-772L or ACPL-072L optocouplers utilize the

latest CMOS IC technology to achieve outstanding speed

performance of minimum 25MBd data rate and 6ns

maximum pulse width distortion.

Basic building blocks of this family of products are a CMOS

LED driver IC, a high speed LED and a CMOS detector IC. A

CMOS logic input signal controls the LED driver IC, which

supplies current to the LED. The detector IC incorporates

an integrated photodiode, a high speed transimpedance

ampliﬁer, and a voltage comparator with an output driver.

Functional Diagram

Features

• Dual voltage operation (3.3V and 5V)

• Allow level shifting functionality

• Support high Speed datarate of 25 MBd

• Wide Temperature operation

• CMOS output and buﬀer input

• Compatible with CMOS and TTL logic level

• Lower power consumption with 3.3V supply

• Good AC performance with lower pulse width

distortion

• Lead-free option available

Speciﬁcations

• 3.3V and 5V CMOS Compatibility

• High Speed: DC to 25 MBd

• 6ns max. Pulse Width Distortion

• 40 ns max. Prop. Delay

• 20 ns max. Prop. Delay Skew

• 10 kV/ms min. Common Mode Rejection

• -40 °C to 105 °C Temperature Range

• Safety and Regulatory Approvals:

UL Recognised for ACPL-072L and Pending UL

Recognised for ACPL-772L

- 5000V

rms

for 1 min. per UL1577 for ACPL-772L

for option 020

- 3750V

rms

for 1 min. per UL1577 for ACPL-072L

CSA Component Acceptance Notice #5

IEC/EN/DIN EN 60747-5-2

– V

IORM

= 630 V

peak

for ACPL-772L Option 060

– V

IORM

= 560 V

peak

for ACPL-072L Option 060

Applications

• Digital Fieldbus Isolation: DeviceNet, Proﬁbus, SDS

• Multiplexed Data Transmission

• General Instrument and Data Acquisition

• Computer Peripheral interface

• Microprocessor System Interface

SHIELD

**V

DD1

NC*

GND

DD2

GND

NC*

LED1

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation, which may be induced by ESD.

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Summary of content (11 pages)

PAGE 1
ACPL-772L and ACPL-072L 3.3V/5V High Speed CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features Available in either an 8-pin DIP or SO-8 style respectively, the ACPL-772L or ACPL-072L optocouplers utilize the latest CMOS IC technology to achieve outstanding speed performance of minimum 25MBd data rate and 6ns maximum pulse width distortion.
PAGE 2
Device Selection Guide 8-Pin DIP (300 Mil) Small Outline SO-8 ACPL-772L ACPL-072L Ordering Information ACPL-072L and ACPL-772L are UL Recognized with 3750 Vrms for 1 minute per UL1577.
PAGE 3
Package Dimensions ACPL-772L 8-Pin DIP Package 9.65 ± 0.25 (0.380 ± 0.010) TYPE NUMBER 8 7 6 7.62 ± 0.25 (0.300 ± 0.010) 5 OPTION 060 CODE* 6.35 ± 0.25 (0.250 ± 0.010) DATE CODE A XXXXV YYWW 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5˚ TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *OPTION 300 AND 500 NOT MARKED. 0.65 (0.025) MAX. 1.080 ± 0.320 (0.043 ± 0.
PAGE 4
ACPL-072L Small Outline SO-8 Package LAND PATTERN RECOMMENDATION 8 7 6 5 XXXV YWW 3.937 ± 0.127 (0.155 ± 0.005) 5.994 ± 0.203 (0.236 ± 0.008) TYPE NUMBER (LAST 3 DIGITS) 7.49 (0.295) DATE CODE PIN ONE 1 2 3 0.406 ± 0.076 (0.016 ± 0.003) 4 1.9 (0.075) 1.270 BSC (0.050) 0.64 (0.025) * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 7˚ 1.524 (0.060) 45 ˚ X 0.432 (0.017) 0~7˚ 0.228 ± 0.025 (0.009 ± 0.001) 0.203 ± 0.102 (0.008 ± 0.
PAGE 5
Solder Reflow Temperature Profile 300 PREHEATING RATE 3˚C + 1 ˚C/- 0.5 ˚C/SEC. REFLOW HEATING RATE 2.5˚C ± 0.5 ˚C/SEC. TEMPERATURE ( ˚ C) 200 PEAK TEMP. 245 ˚C PEAK TEMP. 240 ˚C 2.5˚ C ± 0.5˚C/SEC. 30 SEC. 160 ˚C 150 ˚C 140 ˚C PEAK TEMP. 230˚C SOLDERING TIME 200˚C 30 SEC. 3˚C + 1 ˚C/- 0.5 ˚C 100 PREHEATING TIME 150 ˚C, 90 + 30 SEC. 50 SEC.
PAGE 6
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* ACPL-772L Option 060 ACPL-072L Option 060 Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 450 Vrms I – IV I – IV I – III I – IV I – III Climatic Classification 55/105/21 55/105/21 Pollution Degree (DIN VDE 0110/1.
PAGE 7
Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 +125 °C Ambient Operating Temperature[1] TA –40 +105 °C Supply Voltages VDD1, VDD2 0 6.0 Volts Input Voltage VI –0.5 VDD1 +0.5 Volts Output Voltage VO –0.5 VDD2 +0.5 Volts Average Output Current IO 10 mA Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile Please See Solder Reflow Temperature Profile Section Table 4.
PAGE 8
Table 6. Switching Specifications Test conditions that are not specified can be anywhere within the recommended operating range. The following specifications cover the following power supply combinations: (4.5V≤VDD1≤5.5V, 4.5V≤VDD2≤5.5V), (3V≤VDD1≤3.6V, 3V≤VDD2≤3.6V), (4.5V≤VDD1≤5.5V, 3V≤VDD2≤3.6V) and (3V≤VDD1≤3.6V, 4.5V≤VDD2≤5.5V). All typical specifications are at TA=+25°C, VDD1 = VDD2 = +3.3V.
PAGE 9
31 2.40 29 2.20 27 2.00 25 PWD (ns) Tplh , Tphl (ns) 10. In accordance with UL1577, each ACPL-072L is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 mA). Each ACPL-772L is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 mA). 11.
PAGE 10
Application Information Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Bypassing and PC Board Layout The ACPL-x72L optocouplers are extremely easy to use. No external interface circuitry is required because ACPLx72L uses high speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 7, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.01mF and 0.1mF.
PAGE 11
Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers.