User manual
Table Of Contents
- User Manual
- Starlink SL9003Q
- Digital Studio Transmitter Link
- WARRANTY
- SL9003Q Manual Dwg # 602-12016-01 R: G Revision Levels:
- Using This Manual - Overview
- Section 1 System Features and Specifications
- Section 2 Quick Start
- Section 3 Installation
- Section 4 Operation
- Section 5 Module Configuration
- Section 6 Customer Service
- Section 7 System Information
- Table of Contents
- List of Figures
- List of Tables
- 1 System Features and Specifications
- 2 Quick Start
- 3 Installation
- 4 Operation
- 7.1 Introduction
- 7.2 Front Panel Operation
- 4.3 Screen Menu Navigation and Structure
- 7.4 Screen Menu Summaries
- 4.4.1 Meter
- 4.4.2 System: Card View
- 4.4.3 System: Power Supply
- 4.4.4 System: Info
- 4.4.5 System: Basic Card Setup
- 4.4.6 Factory Calibration
- 4.4.7 SYSTEM: UNIT-WIDE PARAMS
- 4.4.8 System: Date/Time
- 4.4.9 System: Transfer
- 4.4.10 System: External I/O (NMS)
- 4.4.11 Alarms/Faults
- 4.4.12 Radio: Modem Status (QAM)
- 4.4.13 Radio TX Status
- 4.4.14 Radio RX Status
- 4.4.15 Radio TX Control
- 4.4.16 Radio RX Control
- 4.4.17 Radio Modem (QAM) Configure
- 4.4.18 Radio TX Configure
- 4.4.19 Radio RX Configure
- 4.4.20 Radio Modem/TX/RX Copy Function
- 4.5 Intelligent Multiplexer PC Interface Software
- 4.6 NMS/CPU PC Interface Software
- 5 Module Configuration
- 6 Customer Service
- 7 System Description
- 8 Appendices
- Appendix A: Path Evaluation Information
- Appendix B: Audio Considerations
- Appendix C: Glossary of Terms
- Appendix D: Microvolt – dBm – Watt Conversion (50 ohms)
- Appendix E: Spectral Emission Masks
- Appendix F: Redundant Backup with TP64 and TPT-2 Transfer Panels
- Appendix G: Optimizing Radio Performance For Hostile Environments
- Appendix H: FCC APPLICATIONS INFORMATION - FCC Form 601
- Starlink SL9003Q & Digital Composite - 950 MHz Band

7-12 Section 7: System Description
Moseley SL9003Q 602-12016 Revision G
The Audio Decoder module accepts the data stream and the recovered clock from the
backplane (QAM Demod or the MUX). This data (compressed or linear) is fed to the FIFOs
(First In. First Out) buffers. The data is then passed through the FIFOs to an initial data
multiplexer. Sine wave and “zeros” test signal generators are available on the card (switch
selectable) for system testing.
Compressed: The audio decoder add-on card decodes the compressed data per the
appropriate algorithm (ISO/MPEG). This decoded information is then passed on to the Sample
Rate Converter (SRC) via a second data multiplexer.
Linear: Using embedded coding, the linear inputs received are analyzed and then
synchronized for transmission to the Sample Rate Converter via a second data multiplexer.
The second data multiplexer chip selects which of the three inputs (Compressed Audio
Decoder, Linear Frame Sync, or Internal Sine Generator) will be sent to the SRC. As an option,
zeros can also be sent through the multiplexer chip to test the noise floor.
The SRC receives the data stream via the second data multiplexer. This information is
compared to the clock rate determined at switches M7 and M8 for conversion to the final output
decoding segment.
From the SRC, the data is bussed to the AES/EBU encoder for left and right digital audio output,
to the 16 bit D/A converter (located on the Analog Out daughtercard) for the main analog
channel outputs, and to a 12 bit D/A converter that provides an analog output to the bar graph
monitor on the front panel.
The clock source provides the ability to synchronize the various components of the system with
a single device, such as the on-board crystal oscillator, the internal multiplexer clock, the bus,
the AES/EBU input, the trunk, etc. The user can determine whether the card will generate its
own clock or whether it will use a different source’s clock as reference. This information is then
sent to the SRC for conversion of the incoming data to the rate of desired output.