User manual

Section 7: System Description 7-9
Moseley SL9003Q 602-12016 Revision G
All modules (excluding the Front Panel) are interconnected via the Backplane which traverses
the entire width of the unit. The Backplane contains the various communication buses as well
as the redundant transfer circuitry. The power supply levels and status are monitored and the
NMS/CPU card processes the data.
The NMS/CPU card incorporates microprocessor and FPGA logic to configure and monitor the
overall operation of the system via front panel controls, LCD screen menus, status LEDs and
the bar graph display. Module settings are loaded into the installed cards and power-up default
settings are stored in non-volatile memory. LCD screen menu software is uploaded into
memory, providing field upgrade capability. A Windows-based PC interface is available for
connection at the rear panel DATA port.
7.7.1. Receiver Module
BPF
950 MHz
Diplexer
70 MHz
RF Input
944-952 MHz
RF AGC
IF Amp
IF Output
70 MHz
to QAM
Demod
Preamp
AL C
Loop Amp
ALC
Det
At t en
BPF
70 MHz
PLL
Loop
Filter
VCO
880 MHz PLL
Synth
Lock
Data
Clk
Enbl
Ref
ALC Control
12.8 MHz Ref Osc
uP
Synth Level
Synth Lock
NMS
Synth Cl k
Synth Data
Synth Enbl
Figure 7-7 Receiver Module Block Diagram
The receiver handles the traditional down-conversion from the RF carrier to the 70 MHz IF.
Considerations are given to image rejection, intermodulation performance, dynamic range,
agility, and survivability. A separate AGC loop was assigned to the RF front end to prevent
intermodulation and saturation problems associated with reception of high level undesirable
interfering RF signals resulting from RF bandwidth that is much wider than the IF bandwidth.
The linear QAM scheme is fairly intolerant of amplifier overload. These problems are typically
related to difficult radio interference environments that include high power pagers, cellular
phone sites, and vehicle location systems.