Installation manual

Revision F • 3/12
HARRIS CORPORATION
5-5
5 Service
All audio inputs and outputs conform to AES/
EBU standards for digital signals. Each input and
output goes through a 110 ohm balanced AES
signal transformer (T2 - T9). The Main Delay In
(J2) signal goes through a relay (U28) which
couples the signal, through relay U29, to the Main
Delay Out (J4) whenever the HDE-200 is
unpowered.
Each digital input, after being unbalanced by
the AES transformer, goes to an AES receiver chip
(U35 - U37) which time aligns and sample rate
converts the incoming AES or S/PDIF signal to
the internal 44.1 kHz sample rate that the HDE-
200 uses. The serial data output of each AES re-
ceiver goes to the FPGA for internal routing. An
AES Loss alarm is generated if an AES signal is
not present.
The four digital outputs (Main Delay Out, Ref
Mon Out, and the two loop outputs) go through
AES transmitter chips (U18 - U21) that connect
through AES transformers (T4, T5, T8, T9) to J4
(Main Delay Out), J5 (Ref Mon Out), and J1 (the
Post Delay Loop outputs).
The front panel headphone jack is driven from
U22, a combined DAC
(digital to analog con-
verter) and headphone
amp in one chip. The
Front Panel HP Vol-
ume buttons adjust the output level in twenty-five
2 dB steps. The maximum output level is 50 mW
per channel into 16 Ohm headphones.
Refer to the
Hardware chapter for a detailed
description of the 44-pin Remote I-O Logic con-
nection.
5.2.2 FRONT PANEL DISPLAY
The Front Panel Display board connects to the
Interface Controller using a 30-conductor ribbon
cable that carries +5 volts and various control sig-
nals to and from the display. The Interface
Controller’s FPGA drives the Front Panel com-
ponents through two Octal Line Driver/Buffer ICs
(U11 and U12).
The Front Panel Display board has few active
components. Its two 10-Character Intelligent Dis-
plays (DS1 and DS2),
mounted in IC sockets,
indicate Alarm status or
show a selected input or
output signal level. The
displays are self-supporting with built-in signal
decoding and multiplexing circuits and LED driv-
ers. Each display character is a 5x5 dot matrix
with individually addressable LED segments. Two
reference dots (visible between the audio signal
level bargraphs) indicate 0 dBFS (full scale digi-
tal) and -20 dBFS (20 dB below full scale digital).
The seven Front Panel switches connect in an
X-Y matrix to the FPGA chip on the Interface
Controller. The amber LEDs (D1 - D7) indicate