Technical information

OPTO DIO Reference Opto DIO48
Opto DIO48 Memory Map.________________________
The Opto DIO48 has 24 dedicated output lines arranged as
3 eight bit read/write registers, 24 dedicated input lines arranged
as 3 eight bit read only registers and one read/write watchdog
enable/strobe register. Thus the DIO card occupies 7 consecutive
i/o addresses. The output ports are output only, however the
output registers are read/write, writing to them sets the level of
the output lines, reading them provides a read back of the
previously written value. On power up the outputs are zero.
Inputting and outputting data to the Port A, B and C
registers senses and sets the values of the pins at the external
connector. Writes to the watchdog register gate the Port C2 bit 0
and Bit 3 input signals and the signal selected by the BUS
jumper to be gated onto IRQ line or RESET line of the PC.
Reading the watchdog register refreshes the timer and postpones
timeout for another 50milliseconds.
Figure 2-10. Opto DIO48 Memory Map.___________________________________
BASE ADDRESS DEFAULT DEFAULT DIO
OFFSET ADDRESS ADDRESS PORT REGISTER SELECTED
0000 R/W 0308 Hex 776 Dec PORT 0 PORT A#1 OUTPUT PORT A
0001 R/W 0309 Hex 777 Dec PORT 1 PORT B#1 OUTPUT PORT B
0002 R/W 030A Hex 778 Dec PORT 2 PORT C#1 OUTPUT PORT C
0003 R/W 030B Hex 779 Dec PORT 3 WATCH DOG ENABLE REG
READ TO REFRESH WATCHDOG
0004 READ 030C Hex 780 Dec PORT 4 PORT A#2 INPUT PORT A
0005 READ 030D Hex 781 Dec PORT 5 PORT B#2 INPUT PORT B
0006 READ 030E Hex 782 Dec PORT 6 PORT C#2 INPUT PORT C
READ/WRITE WATCH DOG ENABLE REGISTER DEFAULT ADDRESS = 030B Hex
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
WRITE DONT CARE GATE GATE GATE GATE
PORT C2 PORT C2 JUMPER JUMPER
READ ALWAYS 0 BIT 3 BIT 0 BUS BUS
TO IRQ TO IRQ TO IRQ TO RESET
Page 24 Chapter 2