Technical information

OPTO DIO Reference Read This First.

Watch Dog Enable Register._________________________

The watch dog enable register is an 8 bit read write

PC expansion bus IRQ or RESET line. Thus allowing an

interrupt or reset to be generated in the PC. On power up all the

bits are cleared to zero. IE No signals are gated through to the

PC bus. The bit map of the Watch Dog register is given below.

Bits 7-4 are always read back as zero, writing them high or low

has no effect. For compatibility with future versions of this card

bits 7-4 should always be written as 0.

Bit 0 when =1 the watch dog BUS jumper signal is gated to PC

bus RESET line. This line causes a power on reset of the

PC when driven high.

NOTE this line is an output only on many PC’s and so

cannot be used to reset the PC.

Bit 1 when =1 the watch dog BUS jumper signal is gated to the

PC bus IRQ line as selected by the IRQ jumper block.

Bit 2 DIO48 and IN24 ONLY

when =1 the Port C2 bit 0 input signal is gated from the

opto isolator to the IRQ selected by the IRQ jumper block.

Low to high transitions generates a PC interrupt.

OUT24, OUT48 and DIO16 BIT 2 ALWAYS = ZERO.

Bit 3 DIO48 and IN24 ONLY

when =1 the Port C2 bit 3 input signal is gated from the

opto isolator to the IRQ line selected by the IRQ jumper

block. Low to high transition generates the PC interrupt.

OUT24, OUT48 and DIO16 BIT 3 ALWAYS = ZERO.

The IRQ handler should check, by reading the watchdog register,

which interrupt is enabled and service the appropriate function,

eg Watch dog timeout or transition of the Port C lines.

Watch Dog Time Out.___________________

The watch dog times out after 50 milli seconds. The time

out is prevented by a read of the watch dog register, this

refreshes the 50 milli second timeout. Writes to the register do

Page 12 Chapter 1