Technical data

Product Specification
HIF-2121/R5 CAGE CODE: 97896 SCALE: NONE SIZE: A DWG NO: 965-1176-601 REV: D SHEET 126
6.10.7 ATP
The Acceptance Test Procedure (ATP) for the EGPWC will be functional in nature, not designed to characterize the box.
There is no requirement to produce a data sheet showing input thresholds or accuracy of internal processing. The ATP is not
required to test any of the software or databases, other than to verify that they are present and operating. The EGPWC
interface is defined by the Installation Design Guide, where the required inputs and the required output loading are defined.
The most important thing to the customer is reasonable confidence that when the box is given its required inputs it will
produce the stated outputs.
Testing is performed while connected to the EGPWS Ground Support Equipment (GSE) by inserting an ATP cartridge into
the PCMCIA port on the smart cable, connecting the “run from PCMCIA” discrete, and turning the power on. The ATP
cartridge contains code for the central processor that instructs it to report on the inputs and to generate signals used for
checking the outputs. There is no special ATP software support outside of the ATP cartridge.
Refer to the EGPWC Hardware/Software Acceptance Procedure document, 076-0901-001, for EGPWC ATP requirements.
Refer to the applicable ATP, 076-0901-0xx, for requirements and instructions for performing the acceptance test.
6.10.8 BIT Tests
There exists within the EGPWC software Built In Test or BIT capability. Much of this BIT is continuously run, while some
tests are run only as the result of certain events (e.g., power up). Failures are indicated via the EGPWS monitor output
discrete, the ARINC 429 outputs, and system self-test and are saved in the flight history memory. Some BIT failures inhibit
alerts. These cases will be apparent via the response to the system self-test.
For power up and cold start operations all of the possible BIT tests will be run.
At a minimum, BIT functionality will test/monitor the following areas/items:
CPU: The testing of the Central Processing Unit (CPU) will verify the non-random logic, control ROM, on-chip cache, and
translation lookaside buffer (TLB) microprocessor functionality.
RAM: The Random Access Memory (RAM) and the RAM portion of the Non-Volatile Memory (NVM) will be tested to
verify its addressing and data integrity.
Program Memory (ROM): This test performs a 32 bit CRC across the application code memory block and a pass/fail
indication is written to the RS232 port.
Database Memory: This test performs a checksum of database and compares this value to a stored checksum value that was
computed at the time of database release.
Non Volatile Memory (NVM): The non-volatile memory tests verify the read/write integrity of each location of EEPROM.
These tests are non-destructive in that the existing data is restored at the end of the test.
NVM RAM Test: The random access memory portion (RAM) of the non-volatile memory will be tested to verify the
read/write integrity of each location. These tests are non-destructive in that the existing data is restored at the end of the test.
Watch Dog Timer: The Watch Dog Timer test checks for proper operation of the watch dog timer used for software
execution monitoring.
Analog to Digital Converter: Only the Analog to Digital or A/D Converter tests are performed for the analog inputs. These
tests are performed only on installations where analog inputs are utilized.
Voice Generator: Voice Generator tests check the basic voice Digital Signal Processor (DSP) functionality, the ability of the
host processor to boot up and communicate with the voice DSP, and the voice database integrity.
ARINC 429 Transmitter: These tests consist of verifying that the transmitter is able to empty its data buffer and responds
properly to a handshaking flag which is passed between it and the main program software.
ARINC 429 Receiver: The ARINC 429 Receiver tests consist of internal parity checks on the 429 input data. ARINC 429
receiver faults and I/O addressing or data bus errors cause internal parity errors.
Software Task Monitor: This function monitors the various software tasks for fatal errors and takes the appropriate actions
(i.e. shutting down the task) when an error is detected.