Specifications

BMA180
Preliminary data sheet
Bosch Sensortec
Rev. 1.0 Page 63 / - proprietary information - 06 March 2009
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Specifications within this document are preliminary and subject to change without notice. Document is not intended for publication.
8.4 SPI interface (4-wire)
8.4.1 SPI protocol
The SPI interface has a polarity = 1 and SPI phase = 0.
CSB is active low. Data on SDI is latched by BMA180 at SCK rising edge and SDO is changed
at SCK falling edge. Communication starts when CSB goes to low and stops when CSB goes to
high; during these transitions on CSB, SCK must be high. When CSB=1, no SDI change is
allowed when SCK=1 (to avoid any wrong start or stop condition for I
2
C interface).
CSB
SCK
SDI
RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 DI5 DI4 DI3 DI2 DI1 DI0 DI7 DI6
SDO
DO5 DO4 DO3 DO2 DO1 DO0 DO7 DO6
tri-state
Figure 17: 4-wire SPI sequence
When write is required, sequences of 2 bytes are required: 1 control byte to define the address
to be written and the data byte:
Start
RW RW Stop
00010110bit7bit6bit5bit4bit4bit2bit1bit000001011bit7bit6bit5bit4bit4bit2bit1bit0
Register adress (16h) Register adress (0Bh)
CSB
=
0
Control byte Data byte
Data register - adress 1Eh
CSB
=
1
Control byte Data byte
Data register - adress 02h
Figure 18: SPI multiple write
When read is required, the sequence consists in 1 control byte to define first address to be read
followed by data bytes. Addresses are automatically incremented.