User guide

66 6000 Series Programmer's Guide
Setting a bit to zero (0) will enable a particular hardware interrupt. For example, to enable
the IRQ5 interrupt:
#define IRQ5_MASK Øx2Ø /* Bit 5 of 8259 IMR */
outp(0x21, inp(0x21) & ~IRQ5_MASK); /* Enable IRQ5 interrupt */
Because interrupts on the second 8259 controller are software redirected to IRQ2 on the first
8259, we must also enable the IRQ2 interrupt for these interrupts. For example, to enable the
IRQ11 interrupt:
#define IRQ2_MASK ØxØ4 /* Bit 2 on first 8259 IMR */
#define IRQ11_MASK Øx8Ø /* Bit 3 on second 8259 IMR */
outp(0xA1, inp(0xA1) & ~IRQ11_MASK); /* Enable IRQ11 interrupt */
outp(0x21, inp(0x21) & ~IRQ2_MASK); /* Enable IRQ2 interrupt */
➂ Enable
Interrupts in
the AT6nnn
In this third step, you must enable one or more interrupts sources within the AT6nnn. This is
accomplished by writing to the AT6nnn interrupt enable register (AT6nnn base port address +
4). Refer to the illustration below.
Enable Output-Buffer-Has-Data Interrup
t
Enable Input-Buffer-Empty Interrupt
Enable
General-Purpose Interrupt
Enable
Status-Updated Interrupt
Master Interrupt Enable
1
Ø
Ø
7 6 5 4 3 2 1 0
Setting a bit to 1 will enable a particular AT6nnn interrupt. For example, to enable the
general purpose interrupt and status updated interrupt:
#define GP_INTERRUPT 0x04 /* Bit 2 */
#define STATUS_UPDATED 0x08 /* Bit 3 */
#define MASTER 0x10 /* Bit 4 */
int_enable = 0x20; /* Bit 5 */
int_enable = int_enable | MASTER | GP_INTERRUPT | STATUS_UPDATED;
outp(address+4, int_enable);
NOTE
You must keep track of what you write to the AT6nnn interrupt enable register. If you attempt
to read this register, it will not return the status of the interrupt enables. Rather, it will return
the status of each AT6nnn interrupt and more (see ➃ Process Interrupts in ISR below).
➃ Process
Interrupts in
ISR
After enabling the interrupts in the AT6nnn, you must write an interrupt service routine (ISR) to
identify an interrupt and process it. Interrupts can be identified by reading the AT6nnn status
register (AT6nnn base address + 4).
Indicates if data is in AT6nnn's output buffer (Ø = buffer empty, 1 = data available)
Indicates if data is in AT6nnn's input buffer (Ø = buffer empty, 1 = buffer not empty)
Status of AT6nnn general-purpose interrupt (Ø = no interrupt, 1 = interrupt exists)
Status of AT6nnn status-update interrupt (Ø = not updated, 1 = status updated)
Status of AT6nnn master interrupt enable (Ø = no interrupt enabled, 1 = interrupts enabled)
Reserved
Indicates if AT6nnn operating system loaded (Ø = loaded, 1 = not loaded)
Indicates if AT6nnn bus controller loaded (Ø = loaded, 1 = not loaded)
7 6 5 4 3 2 1 0