User guide
64
6000 Series Programmer's Guide
8259 Interrupt
Enable
The PC-AT has two 8259 interrupt
controllers that allow up to 15 different
hardware devices to interrupt the PC-AT.
The first 8259 (at base port address 20H)
handles interrupts IRQ0-IRQ7. The
second 8259 (at base port address A0H)
handles interrupts IRQ8-IRQ15. The
table below lists the PC-AT hardware
interrupts by precedence (from highest to
lowest priority). Programming of the
8259 controller establishes this
precedence.
PC-AT hardware interrupts (IRQ0-
IRQ15) are enabled/disabled by writing to
the 8259 interrupt mask register (8259
base port address + 1).
PC-AT Hardware Interrupt
(highest to lowest priority)
IRQ0 (highest).........................
IRQ1...............................................
IRQ2...............................................
IRQ8...............................................
IRQ9...............................................
IRQ10.............................................
IRQ11.............................................
IRQ12.............................................
IRQ13.............................................
IRQ14.............................................
IRQ15.............................................
IRQ3...............................................
IRQ4...............................................
IRQ5...............................................
IRQ6...............................................
IRQ7 (lowest)..........................
Interrupt
Function
Timer
Keyboard
Reserved
Real-time clock
Reserved
Reserved
Reserved
Reserved
Math co-processor
Hard disk controller
Reserved
COM2 serial
COM1 serial
LPT2 printer
Floppy disk controller
LPT1 printer
80x86 Maskable
Interrupt Enable
The 80x86 processor is capable of disabling all maskable hardware interrupts (IRQ0-IRQ15).
However, it cannot disable a non-maskable interrupt (NMI), such as a memory parity error
interrupt or a divide-by-zero interrupt.
You may want to disable interrupts to protect portions of code from reentrance. For example,
if a function is being executed at the time an interrupt occurs and an interrupt service routine
(ISR) is called, the ISR may attempt to execute that same function. If this happens, the
function is said to be reentered. Keep in mind that most INT 21H functions should not be
called within an ISR because most DOS functions are non-reentrant.
PC-AT maskable hardware interrupts (IRQ0-IRQ15) are enabled/ disabled by the 80x86
instructions STI and CLI. STI sets the 80x86 interrupt flag, enabling interrupts. CLI
clears the 80x86 interrupt flag, disabling interrupts.
80x86 Interrupt
Vectors
Interrupt vectors tell the 80x86 processor where to go to handle an interrupt. Interrupt vectors
are stored in low memory. Because the 80x86 processor works with memory in 64K-byte
chunks called segments, each vector comprises two words: a segment value and an offset into
the segment.
The table below shows the vector address table for PC-AT hardware interrupts. If you decide
to let the AT6nnn use IRQ5, for example, then you must replace the vector at address
0034-0037 with the vector of your interrupt service routine (ISR).
Interrupt Number Vector Address Interrupt Description
08 0020 - 0023 IRQ0 (Timer)
09 0024 - 0027 IRQ1 (Keyboard)
0A 0028 - 002B IRQ2 (Reserved)
0B 002C - 002F IRQ3 (COM2)
0C 0030 - 0033 IRQ4 (COM1)
0D 0034 - 0037 IRQ5 (LPT2)
0E 0038 - 003B IRQ6 (Floppy disk)
0F 003C - 003F IRQ7 (LPT1)
70 01C0 - 01C3 IRQ8 (Real-time clock)
71 01C4 - 01C7 IRQ9 (Reserved)
72 01C8 - 01CB IRQ10 (Reserved)
73 01CC - 01CF IRQ11 (Reserved)
74 01D0 - 01D3 IRQ12 (Reserved)
75 01D4 - 01D7 IRQ13 (Math co-processor)
76 01D8 - 01DB IRQ14 (Hard disk)
77 01DC - 01DF IRQ15 (Reserved)
Fortunately, there are DOS services that permit you to easily modify the interrupt vector table.