Information

BMA280
Data sheet
Page 74
BST-BMA280-DS000-11 | Revision 1.8 | August 2014 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
Register 0x21 (INT_RST_LATCH)
Contains the interrupt reset bit and the interrupt mode selection.
Name
0x21
INT_RST_LATCH
Bit
7
6
5
4
Read/Write
W
R/W
R/W
R/W
Reset
Value
0
0
0
0
Content
reset_int
Reserved
Bit
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
Reset
Value
0
0
0
0
Content
latch_int<3:0>
reset_int: write ‘1’ clear any latched interrupts, or ‘0’ keep latched interrupts
active
reserved: write ‘0’
latch_int<3:0>: ´0000b´ non-latched, ´0001b´ temporary, 250 ms,
´0010b´ temporary, 500 ms, ´0011b´ temporary, 1 s,
´0100b´ temporary, 2 s, ´0101b´ temporary, 4 s,
´0110b´ temporary, 8 s, ´0111b´ latched,
´1000b´ non-latched, ´1001b´ temporary, 250 s,
´1010b´ temporary, 500 s, ´1011b´ temporary, 1 ms,
´1100b´ temporary, 12.5 ms, ´1101b´ temporary, 25 ms,
´1110b´ temporary, 50 ms, ´1111b´ latched
Register 0x22 (INT_0)
Contains the delay time definition for the low-g interrupt.
Name
0x22
INT_0
Bit
7
6
5
4
Read/Write
W
R/W
R/W
R/W
Reset
Value
0
0
0
0
Content
low_dur<7:4>
Bit
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
Reset
Value
1
0
0
1
Content
low_dur<3:0>
low_dur<7:0>: low-g interrupt trigger delay according to [low_dur<7:0> + 1] 2 ms in a
range from 2 ms to 512 ms; the default corresponds to a delay of 20 ms.