Information

BMA280
Data sheet
Page 104
BST-BMA280-DS000-11 | Revision 1.8 | August 2014 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
Example of an I²C read access:
Start
RW ACKS
dummy
ACKS
0 0 1 1 0 0 0 0 X 0 0 0 0 0 1 0
Start
RW ACKS ACKM
ACKM
0 0 1 1 0 0 0 1 X X X X X X X X X X X X X X X X
…
ACKM
ACKM
…
X X X X X X X X X X X X X X X X
…
ACKM
NACK
Stop
…
X X X X X X X X X X X X X X X X
Sr
Slave Adress
Read Data (0x03)
Read Data (0x02)
Control byte
Data byte
Data byte
S
Slave Adress
Register adress (0x02)
P
Data byte
Data byte
Read Data (0x06)
Read Data (0x07)
Data byte
Data byte
Read Data (0x04)
Read Data (0x05)
Figure 20: I²C multiple read
7.2.1 SPI and I²C Access Restrictions
In order to allow for the correct internal synchronisation of data written to the BMA280, certain
access restrictions apply for consecutive write accesses or a write/read sequence through the
SPI as well as I2C interface. The required waiting period depends on whether the device is
operating in normal mode (or standby mode, or low-power mode 2) or suspend mode (or low-
power mode 1).
As illustrated in figure 21, an interface idle time of at least 2 µs is required following a write
operation when the device operates in normal mode (or standby mode, or low-power mode 2).
In suspend mode (or low-power mode 1) an interface idle time of least 450 µs is required.
X-after-Write
Register Update Period
(> 2us / 450us)
Write-Operation X-Operation
Figure 21: Post-Write Access Timing Constraints