Instruction manual

Note: An error condition (standard event register bits 2,3,4 or 5) will always record one or
more errors in the instrument’s error queue. Read the error queue using SYSTem: ERRor?
The standard event register is cleared when:
* You send a *CLS (clear status) command.
* You query the event register using the *ESR? (Event status register) command.
The standard event enable register is cleared when:
* You turn on the power to the instrument.
* You execute a *ESE 0 command.
BIT DEFINITIONS-STANDARD EVENT REGISTER
BIT DESCRIPTION DECIMAL
VALUE DEFINITION
0 Operation Complete 1 All commands prior to and including an *OPC
command have been executed.
1 Not Used 2 The instrument tried to read the output buffer but
it was empty. Or a new command line was
received before a previous query has been read.
Or, both the input and output buffers are full.
2 Query Error 4 The controller tried to read the O/P buffer of the
instrument without giving the Query first or
wrong Channel list was supplied in query.
3 Device Error 8 A Self-Test, Calibration Or Channel TRIP error
occurred.
4 Execution Error 16 An execution error occurred.
5 Command Error 32 A command syntax error has occurred.
6 Not Used 64 Always set to 0.
7 Power On 128 Power has been turned off and on since the last
time the event register was read or cleared.
THE QUESTIONABLE DATA REGISTER
The Questionable Data Register provides information about the FAULTS on the
different CHANNELS of the Source unit. When a CHANNEL TRIP occurs the reason as to
what caused the TRIP on that CHANNEL could be obtained from this register. The CHANNEL
can have Over Voltage trip or Over Current trip or Over Temperature trip. Any or all of these
conditions can be reported in the questionable data summary bit through the enable register.
You must write a decimal value to enable that particular event using the command STATus:
QUEStionable: ENABle < DATA >
43