User`s manual

P4M900-M4
20
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specif ication.
The Choices: Enabled (default), Disabled.
Vlink mode selection
T his item allows you to select Vlink mode.
The Choices: By Auto (default), Mode 0 , Mode 1, Mode 2, Mode 3, Mode 4.
VLink 8X Support
This item allows you to enable or disable VLink 8X support.
The Choices: Enabled (default), Disabled.
VIA PWR Management
The Choices: Enabled (default), Disabled.
Memory Hole
You can reserve this area o f system memory for ISA adap ter ROM. W hen this
area is reserved it cannot be cached. Check the user information of peripherals
that need to use this area of system memo ry for the memory requirements.
The Choices: Disabled (default), Enabled.
System BIOS Cacheable
Selec ting the “Enabled ” optio n allo ws c aching of the system BIOS ROM at
F0000h-FFFFFh, which is able to improve the system performance. However,
any programs that attempts to write to this memory block will cause conflicts
and result in system errors.
The Choices: Enabled (default), Disabled.
Top Performance
The Choices: Disabled (default), Enabled.