User`s manual

A880G+/A785G3+ BIOS Manual
28
South Bridge Co nfig uration
BIOS SETUP UTILITY
Chipset
vxx.xx (C)Copyright 198 5-200x, American Megatre nds, Inc.
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F1
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ESC
OHCI HC(Bus 0 Dev 18 Fn o) [Enabled]
SouthBridge Chipse t Configuration
SB710 CIMx Verison : 4.7.0
OHCI HC(Bus 0 Dev 18 Fn 1) [Enabled]
EHCI HC(Bus 0 Dev 18 Fn 2) [Enabled]
OHCI HC(Bus 0 Dev 19 Fn 0) [Enabled]
OHCI HC(Bus 0 Dev 19 Fn 1) [Enabled]
EHCI HC(Bus 0 Dev 19 Fn 2) [Enabled]
OHCI HC(Bus 0 Dev 20 Fn 5) [Enabled]
OnChip SATA Channe l [Enabled]
OnChip SATA Type [Native IDE]
Option ROM POST De lay [Disabled]
Power Saving Featu res [Disabled]
Options
Disabled
Enabled
OHCI HC(Bus 0 Dev 18/19/20 Fn 0/1/5)
This item allows you to control OHCI host controller. (USB 1.1 Device)
Options: Enabled (Default) / Disabled
EHCI HC(Bus 0 Dev 18/19 Fn 2)
This item allows you to control EHCI host controller. (USB 2.0 Device)
Options: Enabled (Default) / Disabled
OnChip SATA Channel
This option allows you to enable the on-chip Serial ATA.
Options: Enabled (Default) / Disabled
OnChip SATA Type
This option allows you to select the on-chip Serial ATA operation mode.
Options: Native IDE (Default) / RAID / AHCI / Legacy IDE / IDEÆAHCI
Option ROM POST Delay
Options: Disabled (Default) / 1 Second / 2 ~ 7 Seconds