Specifications

VDD_BAT

Input for an internal 1.8 V switched mode regulator combined with output of the internal

battery charger. See chapter 5.3 for detailed description for the charger. When not

powered from a battery, VDD_IO a

nd VDD_BAT can be combined to a single 3.3 V supply

voltage.

VREG_ENA

Enable pin for the internal 1,8 V regulator. This pin is only available with production

version. With the engineering samples VREG_ENA is internally connected to VDD_BAT.

VDD_CHG

Charger input voltage. The charger will start operating when voltage to this pin is applied.

When the charger is not used, this pin should be left floating. See chapter 5.3 for detailed

description of the charg

er.

RES

The RESET pin is an active high reset and is internally filtered using the internal low

frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following

RESET being active. It is recommended that RESET be applied for a period greater than

5ms.

WT32 has an internal reset circuitry, which keeps the reset pin active until supply voltage

has reached stability in the start up. This ensures that supply for the flash memory inside

the WT32 will reach stability before BC4 chip fetches instructions from it. Schematic of the

reset circuitry is shown in figure 3. Rising supply voltage charges the capacitor, which will

activate the reset of WT32. The capacitor discharges through 220 k resistor, which

eventually deactivates the reset. Time constant of the RC circuitry is set in a way that the

supply voltage is safely stabilized before the reset deactivates. Pull-up or pull-down

resistor should not be connected to the reset pin to ensure proper start up of WT32. If the

reset pin of WT32 is in use, the designer should verify that WT32 remains in reset during a

start-up until all supply voltages have stabilized.

Figure 3: WT32 internal reset circuitry

See chapter 4 for detailed description of reset.