WT32 D a t a S h e e t V e r s i o n 1 .
Copyright © 2000-2008 Bluegiga Technologies All rights reserved. Bluegiga Technologies assumes no responsibility for any errors, which may appear in this manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. Bluegiga Technologies’ products are not authorized for use as critical components in life support devices or systems.
VERSION HISTORY Version number: Updates / Changes: 1.1 Bluetooth and FCC qualification IDs added 1.0 Soldering recommendations added. Layout guide fixed. Details at VREG_ENA. Operating temperature range fixed. 0.992 New images added 0.991 Missing pin added to recommended land pattern design 0.99 Microphone biasing recommendation fixed. Voltage regulator enable pin description added. Some small fixes. Layout guidelines for the audio traces added. 0.98 Version history added.
Contents: 1. Ordering Information ................................................................................... 9 2. Block Diagram and Descriptions ................................................................. 10 3. Electrical Characteristics ............................................................................ 12 3.1 Radio Characteristics – Basic Data Rate ........................................................ 17 3.2 Radio Characteristics – Enhanced Data Rate ...................
7.1.1 7.2 Audio Input and Output ........................................................................ 38 Stereo Audio CODEC Interface..................................................................... 39 7.2.1 ADC ................................................................................................... 40 7.2.2 DAC ................................................................................................... 41 7.2.3 IEC 60958 Interface ..........................................
11.1 Soldering Recommendations.................................................................. 64 11.2 Layout Guidelines................................................................................. 64 11.2.1 Audio Layout .................................................................................... 64 11.2.2 Antenna Design ................................................................................ 64 12. WT32 Physical Dimensions .....................................................
Terms & Abbreviations Term or Abbreviation: Explanation: A2DP Advanced Audio Distribution Profile AAC Advanced Audio Coding AVRCP Audio/Video Remote Control Profile Bluetooth Set of technologies providing audio and data transfer over shortrange radio connections CE Conformité Européene DFU Device Firmware Upgrade DSP Digital Signal Processing EDR Enhanced Data Rate FCC Federal Communications Commission HCI Host Controller Interface HFP Hands-Free Profile HID Human Interface Device
PCM Pulse Code Modulation RoHS The Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive (2002/95/EC) SBC Sub Band Codec SPI Serial Peripheral Interface SPP Serial Port Profile UART Universal Asynchronous Transmitter Receiver USB Universal Serial Bus VM Virtual Machine VoIP Voice over Internet Protocol WRAP Wireless Remote Access Platform 7
WT32 Bluetooth® Audio Module DESCRIPTION: FEATURES: WT32 is the latest generation of Bluetooth modules. It provides highest level of integration with integrated 2.4GHz radio, DSP, battery charger, stereo codec, and antenna ready to hit mono and stereo audio applications. WT32 is also ready to support the latest Bluetooth 2.1 standard.
1. ORDERING INFORMATION WT32-A-AI Fimrware AI3 = iWRAP 3.0 C = custom *) HW version A = Chip antenna, industrial temperature range E = W.FL connector, industrial temperature range N = RF pin, industrial temperature range Product series *) Custom firmware refers to any standard firmware with custom parameters (like UART baud rate), custom firmware developed by customer, or custom firmware developed by Bluegiga for the customer.
2. BLOCK DIAGRAM AND DESCRIPTIONS Flash BC05-MM UART/USB RAM Antenna 2.4 GHz Radio Balanced filtter Baseband DSP PIO I/O Audio In/Out MCU PCM/I2S/SPDIF Kalimba DSP SPI XTAL Reset circuitry Figure 1: Block diagram of WT32 BC05-MM The BlueCore05-MM is a single-chip radio and baseband IC for Bluetooth 2.4GHz systems. It provides a fully compliant Bluetooth system to v2.0+EDR of the specification for data and voice.
USB The USB interface is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices. WT32 acts as a USB peripheral, responding to requests from a Master host controller such as a Personal Computer (PC). Synchronous Serial Interface This interface is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be used for system debugging. It can also be used for programming the Flash memory.
3. ELECTRICAL CHARACTERISTICS Absolute maximum ratings Storage temperature Operating temperature VDD_IO VDD_BAT VDD_CHG Terminal voltages Output current from PIOs Min -40 -30 -0.4 -0.4 -0.4 -0.4 Max 85 85 3.6 4.4 6.5 Vdd + 0,4 TBD Unit °C °C V V V V mA The module should not continuously run under these conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device.
Terminal characteristics Min Typ Max Unit VIL input logic level low -0.4 - 0.25xVDD V VIH input logic level high 0.625xVDD - Vdd + 0.3 V VOL output logic level low 0 - 0.125 V VOH output logic level high Reset terminal 0.75xVDD - VDD V 0.64 0.85 1.
Battery charger Battery charger Min VDD_CHG 4.5 Charging mode (VDD_BAT rising to 4.2 V) Supply current (a) Maximum setting Battery trickle charge current (b) (c) Minimum setting Headroom > 0.7 V Maximum battery (e) fast charge current (d) (c) Headroom = 0.3 V Maximum battery Headroom > 0.7 V fast charge current Headroom = 0.3 V (d) (c) Typ - Max 6.5 Unit V 4.
Power Consumption TBD Stereo CODEC Analogue to Digital Converter Parameter Resolution Conditions Input Sample Rate, Fsample Fsample 8 kHz fin = 1kHz 11.025 B/W = kHz 20Hz→20kHz Signal to Noise 16 kHz Ratio, SNR A-Weighted 22.050 THD+N < 1% kHz 150mVpk-pk input 32 kHz 44.
Radio characteristics and general specifications Operating frequency range Specification Note (2400 ... 2483,5) MHz ISM Band Lower quard band 2 MHz Upper quard band 3,5 MHz Carrier frequency 2402 MHz ... 2480 MHz Modulation method Hopping Maximum data rate GFSK (1 Mbps) ∏/4 DQPSK (2Mbps) 8DQPSK (3Mbps) 1600 hops/s, 1 MHz channel space GFSK: Asynchronous, 723.2 kbps / 57.6 kbps Synchronous: 433.9 kbps / 433.9 kbps ∏/4 DQPSK: Asynchronous, 1448.5 kbps / 115.2 kbps Synchronous: 869.
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18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RFTP DGND RESET RTS# CTS# PIO8 PIO7 PIO6 PIO5 PIO4 PCM_IN PCM_OUT PCM_SYNC PCM_CLK DGND SPI_CS# SPI_CLK SPI_MISO SPI_MOSI LED0 VDD_BAT VDD_CHG AGND MIC_BIAS AUDIO_IN _P_RIGHT AUDIO_IN _N_RIGHT AGND AUDIO_IN _P_LEFT AUDIO_IN_N_LEFT AUDIO_OUT _N_RIGHT AUDIO_OUT _P_RIGHT AGND AUDIO_OUT_N_LEFT AUDIO_OUT_P_LEFT RF test point Table 8: WT32 device terminals 4.
VDD_BAT Input for an internal 1.8 V switched mode regulator combined with output of the internal battery charger. See chapter 5.3 for detailed description for the charger. When not powered from a battery, VDD_IO and VDD_BAT can be combined to a single 3.3 V supply voltage. VREG_ENA Enable pin for the internal 1,8 V regulator. This pin is only available with production version. With the engineering samples VREG_ENA is internally connected to VDD_BAT. VDD_CHG Charger input voltage.
PIO0 – PIO10 Programmable digital I/O lines. All PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. Configuration for each PIO line depends on the application. See section 10 “I/O parallel ports” for detailed descriptions for each terminal. Default configuration for all of the PIO lines is input with weak internal pull-up. AIO0 – AIO1 AIOs can be used to monitor analogue voltages such as a temperature sensor for the battery charger.
PCM_OUT A CMOS output with a weak internal pull-down. Used in the PCM (pulse code modulation) interface to transmit digitized audio. The PCM interface is shared with the I2S interface. PCM_IN A CMOS input with a weak internal pull-down. Used in the PCM interface to receive digitized audio. The PCM interface is shared with the I2S interface. PCM_CLK A bi-directional synchronous data clock signal pin with a weak internal pull-down. PCMC is used in the PCM interface to transmit or receive the CLK signal.
AUDIO_IN_P_RIGHT and AUDIO_IN_N_RIGHT Right channel audio inputs. This dual audio input can be configured to be either singleended or fully differential and programmed for either microphone or line input. Route differential pairs close to each other and use a solid dedicated audio ground plane for the audio signals. Audio inputs are sensitive to ESD strikes and thus it is recommended to use ESD clamping diodes at the audio input terminals. Audio signals internal to WT32 use 1.
It is recommended that the LED pad is operated with a pad voltage below 0.5V. In this case, the pad can be thought of as a resistor, RON. The resistance together with the external series resistor will set the current, ILED, in the LED.
5. POWER CONTROL 5.1 Power Supply Configuration WT32 contains an internal battery charger and a switch mode regulator that is mainly used for internal blocks of the module. The module can be powered from a single 3.3 V supply provided that VDD_CHG is floating. Alternatively the module can be powered from a battery connected to VDD_BAT and using an external regulator for VDD_IO. 1.8 V to 3.3 V supply voltage for VDD_IO can be used to give desired signal levels for the digital interfaces of the module.
Figure 6: Example of how to make a power on/off button using latch feature of the internal regulators In figure 6 the internal regulators are latched on at the rising edge, i.e when pressing SW1. One of the PIOs is configured to power hold thus keeping the external regulator on until shut down by pressing SW1 again. 5.3 Battery Charger The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer batteries only.
Fast Charge - Constant Current: entered when the battery voltage is above 2.9V. Fast Charge - Constant Voltage: entered when the battery has reached Vfloat, the charger switches mode to maintain the cell voltage at Vfloat voltage by adjusting the constant charge current. Standby: this is the state when the battery is fully charged and no charging takes place.
UART_RX UART_CTS UART_TX UART_RTS SPI_MOSI SPI_CLK SPI_CS# SPI_MISO PCM_IN PCM_CLK PCM_SYNC PCM_OUT PIO[10:0] Digital input with PD Digital input with PD Digital bi-directional with PU Digital bi-directional with PU Digital input with PD Digital input with PD Digital input with PU Digital tri-state output with PD Digital input with PD Digital bi-directional with PD Digital bi-directional with PD Digital tri-state output with PD Digital bi-directional with PU/PD Table 9: Pin states on reset 29 PD PD PU PU
6. SERIAL INTERFACES 6.1 UART Interface WT32 Universal Asynchronous Receiver Transmitter (UART) interface provides a simple mechanism for communicating with other serial devices using the RS232 standard. The UART interface of WT32 uses voltage levels from 0 to VDD_IO and thus an external transceiver IC is required to meet the voltage level specifications of RS232.
The UART interface is capable of resetting WT32 upon reception of a break signal. A Break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 8. If tBRK is longer than the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This feature allows a host to initialize the system to a known state. Also, WT32 can emit a Break character that may be used to wake the Host.
6.1.1 UART Configuration While RESET is Active The UART interface for WT32 while the chip is being held in reset is tri-state. This will allow the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tri-state when a WT32 reset is deasserted and the firmware begins to run. 6.1.2 UART Bypass Mode Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on WT32 can be used.
6.2 USB Interface WT32 USB devices contain a full speed (12Mbits/s) USB interface that is capable of driving a USB cable directly. No external USB transceiver is required. To match the connection to the characteristic impedance of the USB cable, series resistors must be included to both of the signal lines. These should be of 1% tolerance and the value required may vary between 0 and 20 ohm with 10 ohm being nominal.
PIO R =1.5k USB_D+ WT12 WT32 USB_DUSB_ON Rvb1 Rvb2 Figure 10: USB in self powered mode The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding pin number. In self powered mode, PSKEY_USB_PIO_PULLUP must be set to match with the PIO selected. Note: USB_ON is shared with WT32 PIO terminals (PIO2-PIO7). 6.2.
USB_D+ WT12 WT32 USB_DUSB_ON VBUS GND Voltage regulator Figure 11: USB in bus powered mode 6.2.4 Suspend Current All USB devices must permit the USB controller to place them in a USB Suspend mode. While in USB Suspend, bus powered devices must not draw more than 0.5mA from USB VBUS (self powered devices may draw more than 0.5mA from their own supply). This current draw requirement prevents operation of the radio by bus powered devices during USB Suspend.
10ms max 10ms max USB_DETACH 10ms max No max USB_WAKE_UP Port_Imbedance USB_DPUSB_DN USB_PULL_UP Disconnected Figure 12: USB_DETACH and USB_WAKE_UP Signal 6.2.6 USB Driver A USB Bluetooth device driver is required to provide a software interface between WT32 and Bluetooth software running on the host computer. Suitable drivers are available from www.bluegiga.com/techforum/. 6.2.7 USB 1.1 Compliance WT32 is qualified to the USB specification v1.1, details of which are available from http://www.usb.
6.3 SPI Interface The synchronous serial port interface (SPI) is for interfacing with other digital devices. The SPI port can be used for system debugging. It can also be used for programming the Flash memory. SPI interface is connected by using the MOSI, MISO, CSB and CLK pins. SPI interface can not be used for any application purposes.
7. AUDIO INTERFACES 7.1 Audio Interface The audio interface circuit consists of: Stereo audio CODEC Dual audio inputs and outputs A configurable PCM, I2S or SPDIF interface Figure 13 outlines the functional blocks of the interface. The CODEC supports stereo playback and recording of audio signals at multiple sample rates with a resolution of 16bit. The ADC and the DAC of the CODEC each contain two independent channels. Any ADC or DAC channel can be run at its own independent sample rate.
7.2 Stereo Audio CODEC Interface The main features of the interface are: Stereo and mono analogue input for voice band and audio band Stereo and mono analogue output for voice band and audio band Support for stereo digital audio bus standards such as I2S Support for IEC-60958 standard stereo digital audio bus standards, e.g.
7.2.1 ADC The ADC consists of two second-order Sigma Delta converters allowing two separate channels that are identical in functionality, as shown in Figure 14. Each ADC supports the following sample rates: 8kHz 11.025kHz 16kHz 22.05kHz 24kHz 32kHz 44.1kHz The ADC contains two gain stages for each channel, an analogue and a digital gain stage. The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain settings summarised in Table 13.
Figure 15: ADC analogue amplifier block diagram The second stage of the analogue amplifier shown in Figure 15 has a programmable gain with seven individual 3dB steps. In simple terms, by combining the 24dB gain selection of the microphone input with the seven individual 3dB gain steps, the overall range of the analogue amplifier is approximately -3dB to 42dB in 3dB steps. The overall gain control of the ADC is controlled by a VM function. See iWRAP user guide how to set the gain using iWRAP commands. 7.2.
3 4 5 6 7 8 9 10 11 12 13 14 15 9.5 12 15.5 18 21.5 -24 -20.5 -18 -14.5 -12 -8.5 -6 -2.5 Table 14: DAC digital gain rate selection The DAC analogue amplifier has a programmable gain with seven individual 3dB steps. The overall gain control of the DAC is controlled by a VM function.
Figure 16: Example circuit for SPDIF interface (Co-Axial) Figure 17: Example circuit for SPDIF interface (Optical) 7.2.4 Microphone Input The audio-input is intended for use from 1μA@94dB SPL to about 10μA@94dB SPL. With biasing resistors R1 and R2 equal to 1kΩ, this requires microphones with sensitivity between about –40dBV and –60dBV. The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS will maintain regulation within the limits 0.2 - 1.
2V7 regulator OUT R1 IN VDD_BAT EN MIC_BIAS C1 MIC_A_P C3 MIC C2 MIC_A_N C4 R2 Figure 18: Recommended microphone biasing (left channel shown) The input impedance at AUDIO_IN_N_LEFT, AUDIO_IN_P_LEFT, AUDIO_IN_N_RIGHT and AUDIO_IN_P_RIGHT is typically 6.0kΩ. C1 and C2 should be 150nF if bass roll-off is required to limit wind noise on the microphone. R1 sets the microphone load impedance and is normally in a range of 1 to 2 kΩ.
13 14 15 3.08 3.33 3.57 Table 16: Voltage Output Step Output Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Typical Current (mA) 0.199 0.284 0.336 0.419 0.478 0.529 0.613 0.672 0.754 0.809 0.862 0.948 1.004 1.091 1.142 1.229 Table 17: Current Output Step 7.2.5 Line Input If the input analogue gain is set to less than 21dB, WT32 automatically selects line input mode. In line input mode, the first stage of the amplifier is automatically disabled, providing additional power saving.
Figure 20: Single ended input (left channel shown) 7.2.6 Output Stage The output digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to a 2Mbits/s 5-bit multi-bit bit stream, which is fed into the analogue output circuitry. The output circuit is comprised of a digital to analogue converter with gain setting and an output amplifier. Its class AB output stage is capable of driving a signal on both channels of up to 2V pk-pk differential into a load of 16Ω.
External CODEC contains a side tone circuitry to do this. The side tone hardware is configured through the following PS Keys: PSKEY_SIDE_TONE_ENABLE PSKEY_SIDE_TONE_GAIN PSKEY_SIDE_TONE_AFTER_ADC PSKEY_SIDE_TONE_AFTER_DAC 7.2.6.
7.3 Digital Audio Interface (I2S) The digital audio interface supports the industry standard formats for I2S, left-justified (LJ) or right-justified(RJ). The interface shares the same pins as the PCM interface, which means that each audio bus is mutually exclusive in its usage. Table 18 lists these alternative functions. Figure 22 shows the timing diagram.
Figure 22: Digital audio interface modes The internal representation of audio samples within BlueCore5.Multimedia External is 16bit and data on SD_OUT is limited to 16-bit per channel. Symbol - Parameter SCK Frequency WS Frequency Min - Typ - Max 6.
Figure 23: Digital audio interface slave timing Symbol - Parameter SCK Frequency WS Frequency Min - Typ - Max 6.
7.4 PCM Interface Pulse Code Modulation (PCM) is a standard method used to digitize audio (particularly voice) patterns for transmission over digital communication channels. Through its PCM interface, WT32 has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications. WT32 offers a bi directional digital audio interface that routes directly into the baseband layer of the onchip firmware.
PCM_OUT WT12 PCM_IN WTxx Up to 2048kHz PCM_CLK PCM_SYNC 8kHz Figure 26: WT32 as PCM slave 7.4.2 Long Frame Sync Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When WT32 is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long.
PCM_SYNC PCM_CLK PCM_OUT PCM_IN undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 undefined Figure 28: Short frame sync (shown with 16-bit companded sample) As with Long Frame Sync, WT32 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 7.4.
PCM_SYNC PCM_CLK PCM_OUT PCM_IN undefined 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 undefined Figure 30: GCI interface The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With WT32 in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz. 7.4.6 Slots and Sample Formats WT32 can receive and transmit on any selection of the first four slots following each sync pulse.
13-bit sample PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Audio gain Figure 34: 16-bit slot with 13-bit linear sample and audio gain selected 7.4.7 Additional Features WT32 has a mute facility that forces PCM_OUT to be 0. In Master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running, which some CODECS use to control power down. 7.4.8 PCM CLK and SYNC Generation WT32 has two methods of generating PCM_CLK and PCM_SYNC in master mode.
Name Bit position Description - 0 Set to 0 SLAVE MODE EN 1 0 selects Master mode with internal generation of PCM_CLK and PCM_SYNC. 1 selects Slave mode requiring externally generated PCM_CLK and PCM_SYNC. This should be set to 1 if 48M_PCM_CLK_GEN_EN (bit 11) is set. SHORT SYNC EN 2 0 selects long frame sync (rising edge indicates start of frame), 1 selects short frame sync (falling edge indicates start of frame).
8. I/O PARALLEL PORTS The Parallel Input Output (PIO) Port is a general-purpose I/O interface to WT32. The port consists of eleven programmable, bi-directional I/O lines, PIO[10:0]. Programmable I/O lines can be accessed either through an embedded application running on WT32 or through private channel or manufacturer-specific HCI commands. All PIO lines are configured as inputs with weak pull downs at reset. PIO[2] / USB_PULL_UP (1) The function depends on whether WT32 is a USB or UART capable version.
9. SOFTWARE STACKS WT32 is supplied with Bluetooth v2.0 + EDR compliant stack firmware, which runs on the internal RISC microcontroller. The WT32 software architecture allows Bluetooth processing and the application program to be shared in different ways between the internal RISC microcontroller and an external host processor (if any). The upper layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor. 9.
Notes: More details of iWRAP software and its features can be found from iWRAP User Guide, which can be downloaded from www.bluegiga.com. 9.2 RFCOMM Stack RFCOMM SDP L2CAP HCI LM LC 48kB RAM Baseband MCU USB Host I/O UART Host Radio I/O PCM I/O PCM Figure 36: WRAP THOR RFCOMM stack In the version of the firmware shown in Figure 37, the upper layers of the Bluetooth stack up to RFCOMM are run on-chip.
Full support for all Bluetooth security features up to and including strong (128-bit) encryption. Power Saving: Full support for all Bluetooth power saving modes (Park, Sniff and Hold). Data Integrity: CQDDR increases the effective data rate in noisy environments. RSSI used to minimize interference to other radio devices using the ISM band. Notes: The data rate is with respect to WT32 with basic data rate packets. 9.
separately from Bluegiga or directly form CSR. This code will then execute alongside the main WRAP THOR firmware. The user is able to make calls to the WRAP THOR firmware for various operations. WRAP THOR firmware is not equal to iWRAP firmware, which on the contrary does not allow users to run their own firmware in the module.
10. ENHANCED DATA RATE EDR has been introduced to provide 2x and optionally 3x data rates with minimal disruption to higher layers of the Bluetooth stack. CSR supports both of the new data rates, with WT32. WT32 is compliant with revision v2.0.E.2 of the specification. 10.1 Enhanced Data Rate Baseband At the baseband level, EDR uses the same 1.6kHz slot rate as basic data rate and therefore the packets can be 1, 3, or 5 slots long as per the basic data rate.
10.3 8DQPSK 8-state Differential Phase-Shift Keying Three bits determine phase shift between consecutive symbols.
11. LAYOUT AND SOLDERING CONSIDERATIONS 11.1 Soldering Recommendations WT32 is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. Consult the datasheet of particular solder paste for profile configurations.
Figure 39: Recommended layout for the ground planes around the module. Figure 40: Bottom side layout of the module. Any via in the module can cause a short if placed directly above bare copper on a PCB.
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Figure 44: Reel appearance and dimensions 68
14. CERTIFICATIONS WT32 is compliant to the following specifications. 14.1 Bluetooth WT32 module is Bluetooth qualified and listed as an end product. If not modified in any way, it is a complete Bluetooth entity, containing software and hardware functionality as well as the whole RF-part including the antenna. This practically translates to that if the module is used without modification of any kind, it does not need any Bluetooth approval work.
14.2 FCC Federal Communications Commission (FCC) Statement 15.21 You are cautioned that changes or modifications not expressly approved by the part responsible for compliance could void the user’s authority to operate the equipment. 15.105(b) This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
14.3 CE WT32 meets the requirements of the standards below and hence fulfills the requirements of EMC Directive 89/336/EEC as amended by Directives 92/31/EEC and 93/68/EEC within CE marking requirement. Electromagnetic emission EN 301 489-17 V.1.2.
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16. CONTACT INFORMATION Sales: sales@bluegiga.com Technical support: support@bluegiga.com http://techforum.bluegiga.com Orders: orders@bluegiga.com Head Office / Finland: Phone: Fax: +358-9-4355 060 +358-9-4355 0660 Street Address: Sinikalliontie 11 02630 ESPOO FINLAND Postal address: P.O. BOX 120 02631 ESPOO, FINLAND Sales Office / USA: Phone: (781) 556-1039 Street address: Bluegiga Technologies, Inc.
