Specifications

Functional Description
30-Dec-2010 CM-X300 Reference Guide Rev 1.31 45
3.3.19.6 PWM Control Register (PWMCRx)
The PWM Control register (PWMCRx), defined in Table 47, configures the behavioral
characteristics of the PWM shutdown response and the divisor for the input clocks to the
PWM control unit that configures the frequency of the scaled counter clock.
This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits.
Table 47 PWM Control Register
Bits
Access
Name
Description
31:7
–
–
Reserved
6
R/W
SD
Pulse Width Modulator Shutdown Mode:
0 = Graceful shutdown of PWMx when the PXA3xx
processor family stops the clocks to the PWM.
1 = Abrupt shutdown of PWMx when the PXA3xx
processor family stops the clocks to the PWM.
5:0
R/W
PRESCALE
The scaled counter clock frequency is:
PSCLK_PWMx / (PRESCALEx + 1)
3.3.19.7 PWM Duty Cycle Register (PWMDCRx)
The PWMx Duty Cycle register (PWMDCRx), defined in Table 48, configures the duty
cycle of the PWMx_OUT signal.
PWMDCRx[DCYCLE] specifies the number of scaled counter clocks that PWMx_OUT is
asserted during each cycle of the PWMx_OUT. Refer to Section 3.3.19.4 for details on
calculating the value of PWMDCRx[DCYCLE].
If PWMDCRx[FD] is set, PWMx_OUT remains high until PWMDCRx[FD] is cleared.
This results in a duty cycle of 100%. Typically, PWMDCRx[FD] is cleared and the duty
cycle of PWMx_OUT is a function of PWMDCRx[DCYCLE].
This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits.
Table 48 PWM Duty Cycle Register
Bits
Access
Name
Description
31:11
–
–
Reserved
10
R/W
FD
Full Duty Cycle:
0 = PWMx_OUT is determined by DCYCLE value.
1 = PWMx_OUT is continuously asserted.
9:0
R/W
DCYCLE
Duty Cycle of PWMx_OUT:
0 = PWMx_OUT is continuously de-asserted.
1 = PWMx_OUT is high for the number of 13-MHz
clock periods equal to
PWMDCRx[DCYCLE] x (PWMCRx[PRESCALE]+1),
If FD is set, DCYCLE has no effect on the output of
PWM
3.3.19.8 PWM Period Control Register (PWMPCRx)
The Period Control registers (PWMPCRx), defined in This is a read/write register. Ignore
reads from reserved bits. Write 0b0 to reserved bits.
Table 49, configures the cycle time of the PWMx_OUT signal.
PWMPCRx[PV] specifies the number of scaled counter clocks (plus one) in each cycle of
the PWMx_OUT. Refer to Section 3.3.19.4 for details on calculating the value of
PWMPCRx[PV].
If this register is cleared the PWMx_OUT signal maintains in a high state.
This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits.